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1. 发明授权

US07263122B2 Receiver based decision feedback equalization circuitry and techniques 有权
标题翻译：基于接收机的判决反馈均衡电路和技术
公开(公告)号：US07263122B2
公开(公告)日：2007-08-28
申请号：US10630991
申请日：2003-07-29
申请人： John T. Stonick , Jeffrey L. Sonntag , Daniel Keith Weinlader
发明人： John T. Stonick , Jeffrey L. Sonntag , Daniel Keith Weinlader
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H04L2025/0349
摘要： In one aspect, the present invention is directed to a technique of, and circuitry and system for enhancing the performance of data communication systems using receiver based decision feedback equalization circuitry. In one embodiment, the equalization circuitry and technique employs a plurality of data slicers (for example, two) to receive an analog input and output a binary value based on the reference or slicer level. The output of the data slicers is provided to logic circuitry to determine whether the analog input was a binary high or binary low. In those instances where the data slicers “agree” and both indicate either a high or a low, the logic circuitry outputs the corresponding binary value. In those instances where the data slicer do not “agree”—that is, where one data slicer indicates the input to be a binary or logic high value and the other data slicer indicates the input to be a binary or logic low value, in one embodiment, the logic circuitry outputs the complement of the previous binary value. In another embodiment, the logic circuitry selects the output from the slicer that changed its output from the previous binary value. In yet another embodiment where the slicers do not “agree”, the logic circuitry selects the decision of the data slicer with higher slicer value if the previous binary value was “high”, or selects the decision of the data slicer with the lower slicer value if the previous binary value was “low”. The data slicers employ slicer levels that may be fixed, pre-programmed, predetermined, preset, changed, modified, optimized, enhanced and/or programmed or re-programmed (for example, adaptively) before or during operation of the decision feedback equalization circuitry.
摘要翻译：一方面，本发明涉及一种使用基于接收机的判决反馈均衡电路来增强数据通信系统的性能的技术和电路和系统。在一个实施例中，均衡电路和技术采用多个数据限幅器（例如，两个）来接收模拟输入并基于参考或限幅器电平输出二进制值。数据限幅器的输出被提供给逻辑电路，以确定模拟输入是二进制高还是二进制低。在数据限幅器“同意”并且都表示高电平或低电平的情况下，逻辑电路输出相应的二进制值。在数据限幅器不“同意”的情况下，即一个数据限幅器将输入指示为二进制值或逻辑高电平值，另一个数据限幅器将输入指示为二进制值或逻辑低电平值，逻辑电路输出先前二进制值的补码。在另一个实施例中，逻辑电路选择来自限幅器的输出，其从先前的二进制值改变其输出。在限幅器不“同意”的又一个实施例中，如果先前的二进制值为“高”，则逻辑电路选择具有较高限幅器值的数据限幅器的判定，或者选择具有较低限幅器值的数据限幅器的判定如果先前的二进制值为“低”。数据限幅器采用可在固定，预编程，预定，预设，改变，修改，优化，增强和/或编程或重新编程（例如，自适应地）自适应地在决策反馈均衡电路的操作期间的限幅器电平。

2. 发明授权

US07230506B2 Crosstalk reduction for a system of differential line pairs 失效
标题翻译：差分线对系统的串扰降低
公开(公告)号：US07230506B2
公开(公告)日：2007-06-12
申请号：US10682617
申请日：2003-10-09
申请人： William Beale , John T. Stonick , Jeffrey L. Sonntag
发明人： William Beale , John T. Stonick , Jeffrey L. Sonntag
IPC分类号： H01P3/04
CPC分类号： H05K1/0245 , H01P3/02 , H05K1/0228 , H05K1/0248 , H05K1/115 , H05K2201/044 , H05K2201/09236 , H05K2201/09263
摘要： A technique is presented for minimizing crosstalk between adjacent differential signal pairs in communications. A backplane embodiment wherein the backplane includes a plurality of differential signal line pairs, is presented. A first differential signal line pair can include a first differential signal line and a second differential signal line. The backplane can have the first differential signal line connected between first and second vias. The second differential signal line can be connected between third and fourth vias. A third signal line can be connected between fifth and sixth vias. The first via can be spatially adjacent to the fifth via such that a signal on the third signal line is coupled to the first differential signal line and the fourth via can be spatially located adjacent to the sixth via such that a signal on the third signal line is coupled to the second differential signal line.
摘要翻译：提出了一种用于最小化通信中相邻差分信号对之间的串扰的技术。提出了背板实施例，其中背板包括多个差分信号线对。第一差分信号线对可以包括第一差分信号线和第二差分信号线。背板可以具有连接在第一和第二通孔之间的第一差分信号线。第二差分信号线可以连接在第三和第四通孔之间。第三个信号线可以连接在第五和第六个通孔之间。第一通孔可以在空间上与第五通孔相邻，使得第三信号线上的信号耦合到第一差分信号线，并且第四通孔可以在空间上位于第六通孔附近，使得第三信号线上的信号耦合到第二差分信号线。

3. 发明授权

US08477898B2 Highly flexible fractional N frequency synthesizer 有权
$Highly flexible fractional N frequency synthesizer$
标题翻译：高灵活度的分数N频率合成器
公开(公告)号：US08477898B2
公开(公告)日：2013-07-02
申请号：US12819683
申请日：2010-06-21
申请人： James P. Flynn , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin , Dino A. Toffolon , Jasjeet Singh
发明人： James P. Flynn , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin , Dino A. Toffolon , Jasjeet Singh
IPC分类号： H03D3/24
CPC分类号： H03L7/183 , H03L7/081
摘要： One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.
摘要翻译：本发明的一个实施例提供了一种用于合成分数频率的锁相环（PLL）。 PLL可以包括1 / N分频器，压控振荡器（VCO），可编程相位混频器和相位检测器。可编程相位混频器可以耦合在VCO的输出端和分频器的输入端之间，其中可编程相位混频器配置成从VCO接收输出时钟信号，并通过改变相位产生频率为f1的第一时钟信号的输出时钟信号。分频器被配置为从可编程相位混合器接收第一时钟信号，并产生频率为f2 = f1 / N的第二时钟信号。相位检测器可以接收参考时钟信号和第二个时钟信号作为输入，并且相位检测器的输出可用于产生VCO的控制电压。

4. 发明申请

US20110311009A1 PATTERN AGNOSTIC ON-DIE SCOPE 有权
标题翻译：模式合成模型
公开(公告)号：US20110311009A1
公开(公告)日：2011-12-22
申请号：US12819660
申请日：2010-06-21
申请人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H04L7/00
CPC分类号： H04L1/205 , G01R13/0218
摘要： An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.
摘要翻译：描述了一个模内范围。在线范围可以包括一个或多个范围限幅器，相位扫描电路，电压扫描电路和眼图数据收集电路。时钟和数据恢复电路可以接收输入信号，并输出恢复的时钟信号和恢复的比特流。相位扫描电路可以接收恢复的时钟信号，并通过向恢复的时钟信号添加相位偏移来输出示波器时钟信号。示波器限幅器可以接收电压阈值，示波器时钟信号和输入信号，并输出示波器位流。眼图数据收集电路可以检测恢复的比特流中的一个或多个比特模式，并且单独或部分地基于范围比特流和恢复的比特流来修改一个或多个范围计数器的值。

5. 发明申请

US20110309857A1 CIRCUITRY FOR MATCHING THE UP AND DOWN IMPEDANCES OF A VOLTAGE-MODE TRANSMITTER 有权
标题翻译：用于匹配电压模式发射器的上下移动电路的电路
公开(公告)号：US20110309857A1
公开(公告)日：2011-12-22
申请号：US12819650
申请日：2010-06-21
申请人： James P. Flynn , Junqi Hua , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H03F1/56 , H03F2200/387 , H04L25/028
摘要： Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.
摘要翻译：本发明的一些实施例提供一种电压模式发射机。发射机可以包括配置电路，偏置电路和一组驱动器片。每个驱动器片可以包括驱动输出值的驱动器晶体管。每个驱动器片的输出可以与发射器的输出直接或电容耦合。每个驱动器片还可以包括串联耦合到至少一些驱动晶体管的一个或多个阻抗匹配晶体管。配置电路可以配置驱动器片段的子集，使得发射机的向下（或向上）阻抗在期望阻抗值的第一公差内。偏置电路可以偏置驱动器片段子集中的每个驱动器片中的一个或多个阻抗匹配晶体管，使得上（或下））阻抗在下（或向上）阻抗的第二容限内。

6. 发明授权

US08589708B2 Reducing power consumption in clock and data recovery systems 有权
标题翻译：降低时钟和数据恢复系统的功耗
公开(公告)号：US08589708B2
公开(公告)日：2013-11-19
申请号：US12797411
申请日：2010-06-09
申请人： James P. Flynn , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： G06F1/32 , G06F1/06
CPC分类号： H03L7/093
摘要： Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system.
摘要翻译：一些实施例提供了一种从模拟信号中恢复时钟和数据信息的时钟和数据恢复（CDR）系统。 CDR系统可以包括作为积分比例控制回路的一部分的积分路径和比例路径。积分路径可以用于跟踪嵌入在模拟信号中的时钟信号中的频率变化，而比例路径可以用于跟踪嵌入在模拟信号中的时钟信号中的相位变化。比例路径可以以第一时钟频率执行，而积分路径可以在低于第一时钟频率的第二时钟频率下执行，以减少CDR系统的功耗。

7. 发明申请

US20110310942A1 HIGHLY FLEXIBLE FRACTIONAL N FREQUENCY SYNTHESIZER 有权
标题翻译：高灵敏度的零频合成器
公开(公告)号：US20110310942A1
公开(公告)日：2011-12-22
申请号：US12819683
申请日：2010-06-21
申请人： James P. Flynn , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin , Dino A. Toffolon , Jasjeet Singh
发明人： James P. Flynn , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin , Dino A. Toffolon , Jasjeet Singh
IPC分类号： H03L7/00 , H04L7/00 , H04B1/38
CPC分类号： H03L7/183 , H03L7/081
摘要： One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.
摘要翻译：本发明的一个实施例提供了一种用于合成分数频率的锁相环（PLL）。 PLL可以包括1 / N分频器，压控振荡器（VCO），可编程相位混频器和相位检测器。可编程相位混频器可以耦合在VCO的输出端和分频器的输入端之间，其中可编程相位混频器配置成从VCO接收输出时钟信号，并通过改变相位产生频率为f1的第一时钟信号的输出时钟信号。分频器被配置为从可编程相位混合器接收第一时钟信号，并产生频率为f2 = f1 / N的第二时钟信号。相位检测器可以接收参考时钟信号和第二个时钟信号作为输入，并且相位检测器的输出可用于产生VCO的控制电压。

8. 发明授权

US08526551B2 Multiple-input, on-chip oscilloscope 有权
标题翻译：多路输入，片上示波器
公开(公告)号：US08526551B2
公开(公告)日：2013-09-03
申请号：US12791755
申请日：2010-06-01
申请人： James P. Flynn , Junqi Hua , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H03D1/04
CPC分类号： G01R13/0272 , G01R31/2884 , G01R31/3171 , H04L25/03878 , H04L27/01
摘要： An integrated circuit that includes a receive data path is described. The receive data path: equalizes a received analog signal, converts the resulting equalized analog signal to digital data values based on a clock signal, and recovers the clock signal in the digital data values. The integrated circuit also includes an on-chip oscilloscope. The oscilloscope includes: two comparators, a phase rotator that outputs an oscilloscope clock signal whose phase can be varied relative to that of the recovered clock signal, and an offset circuit that outputs a voltage offset. Based on the voltage offset and the oscilloscope clock signal, the comparators output digital values which can be used to determine eye patterns that correspond to the analog signal before and after equalization. The eye patterns can then be correlated with an error rate associated with the received data.
摘要翻译：描述了包括接收数据路径的集成电路。接收数据路径：对接收到的模拟信号进行均衡，基于时钟信号将所得到的均衡模拟信号转换为数字数据值，并恢复数字数据值中的时钟信号。该集成电路还包括片上示波器。示波器包括：两个比较器，一个相位旋转器，输出示波器时钟信号，相位可以相对于恢复的时钟信号的相位变化;以及偏移电路，输出电压偏移。基于电压偏移和示波器时钟信号，比较器输出可用于确定与均衡前后的模拟信号相对应的眼图的数字值。然后眼图可以与与接收的数据相关联的错误率相关联。

9. 发明授权

US08208591B2 Method and apparatus for performing adaptive equalization 有权
标题翻译：用于执行自适应均衡的方法和装置
公开(公告)号：US08208591B2
公开(公告)日：2012-06-26
申请号：US12819629
申请日：2010-06-21
申请人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H04B1/10
CPC分类号： H04L25/03019 , H04L2025/03617 , H04L2025/03656 , H04L2025/037
摘要： Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.
摘要翻译：描述了用于适配和/或优化接收机的均衡器的系统和技术。可以通过修改一个或多个均衡参数来调整均衡器的行为。在适应和/或优化过程的开始时，系统可以确定一个或多个均衡参数的鲁棒的初始值。然后，系统可以通过迭代地调整一个或多个均衡参数来适应和/或优化均衡器。具体来说，在每个迭代中，系统可以使用接收机的时钟和数据恢复（CDR）电路来确定与一个或多个数据模式相关联的早期和晚期数据转换的数量。接下来，系统可以调整一个或多个均衡参数，使得对于一个或多个数据模式中的每个数据模式，早期数据转换的数量与后期数据转换的数量之间的比率基本上等于期望值。

10. 发明申请

US20110310947A1 METHOD AND APPARATUS FOR PERFORMING ADAPTIVE EQUALIZATION 有权
标题翻译：用于执行自适应均衡的方法和装置
公开(公告)号：US20110310947A1
公开(公告)日：2011-12-22
申请号：US12819629
申请日：2010-06-21
申请人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
发明人： James P. Flynn , Junqi Hua , Robert B. Lefferts , Richard H. Steeves , John T. Stonick , Daniel K. Weinlader , Jianping Wen , Skye Wolfer , David A. Yokoyama-Martin
IPC分类号： H03H7/30
CPC分类号： H04L25/03019 , H04L2025/03617 , H04L2025/03656 , H04L2025/037
摘要： Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.
摘要翻译：描述了用于适配和/或优化接收机的均衡器的系统和技术。可以通过修改一个或多个均衡参数来调整均衡器的行为。在适应和/或优化过程的开始时，系统可以确定一个或多个均衡参数的鲁棒的初始值。然后，系统可以通过迭代地调整一个或多个均衡参数来适应和/或优化均衡器。具体来说，在每个迭代中，系统可以使用接收机的时钟和数据恢复（CDR）电路来确定与一个或多个数据模式相关联的早期和晚期数据转换的数量。接下来，系统可以调整一个或多个均衡参数，使得对于一个或多个数据模式中的每个数据模式，早期数据转换的数量与后期数据转换的数量之间的比率基本上等于期望值。

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