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1. 发明授权

US08975970B2 Producing a desired frequency using a controlled oscillator with known temperature sensitivity 有权
标题翻译：使用已知温度敏感度的受控振荡器产生所需的频率
公开(公告)号：US08975970B2
公开(公告)日：2015-03-10
申请号：US12774453
申请日：2010-05-05
申请人： Jeffrey L. Sonntag
发明人： Jeffrey L. Sonntag
IPC分类号： H03L7/00 , H03L1/02
CPC分类号： H03L7/00
摘要： A controlled oscillator is tuned to produce a desired, temperature independent frequency. A first frequency ratio is determined between a first frequency of the output signal generated by the controlled oscillator and a frequency of an output signal from another oscillator. The first frequency is determined based on a sensed temperature. A desired frequency of the output signal of the controlled oscillator is used to determine a desired frequency ratio between the desired frequency and the frequency of the output signal from the other oscillator. The controlled oscillator is tuned and the frequency ratio measured until the tuning has caused the desired frequency ratio to be achieved, thereby causing the controlled oscillator to provide the desired frequency.
摘要翻译：受控振荡器被调谐以产生期望的与温度无关的频率。在由受控振荡器产生的输出信号的第一频率和来自另一个振荡器的输出信号的频率之间确定第一频率比。第一个频率是基于感测的温度来确定的。使用受控振荡器的输出信号的期望频率来确定期望频率与来自另一个振荡器的输出信号的频率之间的期望频率比。调节受控振荡器，并测量频率比，直到调谐已经达到所需的频率比，从而使受控振荡器提供所需的频率。

2. 发明授权

US08918067B2 Servo loop for quality-factor compensation in a capacitor array 有权
标题翻译：用于电容器阵列中质量因子补偿的伺服回路
公开(公告)号：US08918067B2
公开(公告)日：2014-12-23
申请号：US12774459
申请日：2010-05-05
申请人： James F. Parker , Jeffrey L. Sonntag
发明人： James F. Parker , Jeffrey L. Sonntag
IPC分类号： H03C1/52 , H04B1/04 , H03H11/30
CPC分类号： H04B1/0458 , H03H11/30
摘要： The impedance of the elements of a capacitor array in the transmitter is kept substantially constant over changes in process, temperature, and supply voltage. The impedance is maintained substantially constant by compensating a gate voltage supplied to switches in each element of the capacitor array to adjust for changes in temperature and supply voltage to thereby maintain a substantially constant RC product for each unit element in the capacitor array and thereby improve the quality factor of the capacitor array.
摘要翻译：变送器中电容器阵列的元件的阻抗在过程，温度和电源电压的变化上保持基本恒定。通过补偿提供给电容器阵列的每个元件中的开关的栅极电压来阻抗来保持基本恒定，以调整温度和电源电压的变化，从而为电容器阵列中的每个单位元件保持基本上恒定的RC积，从而改善电容阵列的品质因数。

3. 发明申请

US20130169340A1 CAPACITIVE TOUCH SENSOR INTERFACE 审中-公开
标题翻译：电容触摸传感器接口
公开(公告)号：US20130169340A1
公开(公告)日：2013-07-04
申请号：US13340772
申请日：2011-12-30
申请人： Yonghong Tao , Daniel J. Cooley , Jeffrey L. Sonntag , Hong Lee Koo
发明人： Yonghong Tao , Daniel J. Cooley , Jeffrey L. Sonntag , Hong Lee Koo
IPC分类号： G06G7/18 , G01R27/26
CPC分类号： G06F3/044 , G06F3/0416
摘要： A technique includes charging and discharging a capacitive sensor of a display. The technique includes regulating currents that are associated with the charging and discharging based at least in part on a reference time interval and determining a capacitance sensed by the capacitive sensor based at least in part on the regulating.
摘要翻译：一种技术包括对显示器的电容式传感器进行充电和放电。该技术包括至少部分地基于参考时间间隔调节与充电和放电相关联的电流，并且至少部分地基于调节来确定由电容传感器感测的电容。

4. 发明申请

US20120250746A1 TRANSITION INTERVAL CODING FOR SERIAL COMMUNICATION 有权
标题翻译：用于串行通信的过渡间隔编码
公开(公告)号：US20120250746A1
公开(公告)日：2012-10-04
申请号：US13076155
申请日：2011-03-30
申请人： Jeffrey L. Sonntag
发明人： Jeffrey L. Sonntag
IPC分类号： H04B17/00
CPC分类号： H04L25/4902 , H04L25/061
摘要： A one-wire transmission protocol utilizes transition interval coding in which a value of a transmitted symbol is determined by comparing an interval length between the voltage transition associated with the transmitted symbol and a prior voltage transition on the communication link, to a threshold transition interval provided to the receiving device during the transmission sequence that includes the transmitted symbol. If the interval length of the symbol is below the transition interval threshold, the symbol is determined to be a first value and if the interval length of the symbol is above the transition interval threshold, the symbol is determined to be a second value. The transition interval threshold is provided in a start sequence that includes at least two transitions. The threshold transition interval width is based on one or more transition intervals determined during the start sequence.
摘要翻译：一线传输协议使用转换间隔编码，其中通过将与发送符号相关联的电压转换与通信链路上的先前电压转换之间的间隔长度与所提供的阈值转换间隔进行比较来确定发送符号的值在包括发送符号的发送序列期间到接收设备。如果符号的间隔长度低于转换间隔阈值，则将符号确定为第一值，并且如果符号的间隔长度高于转换间隔阈值，则将该符号确定为第二值。过渡间隔阈值以包括至少两个转变的起始序列提供。阈值转换间隔宽度基于在开始序列期间确定的一个或多个过渡间隔。

5. 发明申请

US20120043999A1 MEMS STABILIZED OSCILLATOR 审中-公开
标题翻译： MEMS稳定振荡器
公开(公告)号：US20120043999A1
公开(公告)日：2012-02-23
申请号：US13285608
申请日：2011-10-31
申请人： Emmanuel P. Quevy , Susumu Hara , Jeffrey L. Sonntag
发明人： Emmanuel P. Quevy , Susumu Hara , Jeffrey L. Sonntag
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L1/022
摘要： A voltage controlled crystal oscillator (VCXO) is locked to a MEMS oscillator with a variable frequency ratio that is a function of a sensed temperature. That allows the long-term stability of the MEMS oscillator and temperature compensation to be reflected in a VCXO output signal having good short-term stability.
摘要翻译：压控晶体振荡器（VCXO）被锁定到具有可变频率比的MEMS振荡器，该频率比是感测温度的函数。这允许MEMS振荡器的长期稳定性和温度补偿反映在具有良好短期稳定性的VCXO输出信号中。

6. 发明申请

US20110279096A1 METHOD AND APPARATUS FOR POWERING A HIGH CURRENT SYSTEM FROM A RESISTIVE ELECTRICAL STORAGE DEVICE 审中-公开
标题翻译：用于从电阻储存装置供电高电流系统的方法和装置
公开(公告)号：US20110279096A1
公开(公告)日：2011-11-17
申请号：US12781095
申请日：2010-05-17
申请人： Jeffrey L. Sonntag
发明人： Jeffrey L. Sonntag
IPC分类号： H02J7/00
CPC分类号： H02J7/34 , H02J7/345
摘要： An apparatus includes an energy storage device having an equivalent series resistance coupled to a power supply node. The apparatus includes a first capacitor having an equivalent series resistance substantially lower than the equivalent series resistance of the energy storage device. In a first mode of the apparatus, the first capacitor is operative to receive charge from the power supply node. In a second mode of the apparatus, the first capacitor is operative to deliver current to a load. In a third mode of the apparatus, the power supply node is operative to deliver a second current to the load. The second current is substantially less than the first current.
摘要翻译：一种装置包括具有耦合到电源节点的等效串联电阻的能量存储装置。该装置包括具有基本上低于储能装置的等效串联电阻的等效串联电阻的第一电容器。在装置的第一模式中，第一电容器用于从电源节点接收电荷。在装置的第二模式中，第一电容器用于将电流传送到负载。在装置的第三模式中，电源节点可操作地将第二电流传送到负载。第二电流基本上小于第一电流。

7. 发明授权

US07230506B2 Crosstalk reduction for a system of differential line pairs 失效
标题翻译：差分线对系统的串扰降低
公开(公告)号：US07230506B2
公开(公告)日：2007-06-12
申请号：US10682617
申请日：2003-10-09
申请人： William Beale , John T. Stonick , Jeffrey L. Sonntag
发明人： William Beale , John T. Stonick , Jeffrey L. Sonntag
IPC分类号： H01P3/04
CPC分类号： H05K1/0245 , H01P3/02 , H05K1/0228 , H05K1/0248 , H05K1/115 , H05K2201/044 , H05K2201/09236 , H05K2201/09263
摘要： A technique is presented for minimizing crosstalk between adjacent differential signal pairs in communications. A backplane embodiment wherein the backplane includes a plurality of differential signal line pairs, is presented. A first differential signal line pair can include a first differential signal line and a second differential signal line. The backplane can have the first differential signal line connected between first and second vias. The second differential signal line can be connected between third and fourth vias. A third signal line can be connected between fifth and sixth vias. The first via can be spatially adjacent to the fifth via such that a signal on the third signal line is coupled to the first differential signal line and the fourth via can be spatially located adjacent to the sixth via such that a signal on the third signal line is coupled to the second differential signal line.
摘要翻译：提出了一种用于最小化通信中相邻差分信号对之间的串扰的技术。提出了背板实施例，其中背板包括多个差分信号线对。第一差分信号线对可以包括第一差分信号线和第二差分信号线。背板可以具有连接在第一和第二通孔之间的第一差分信号线。第二差分信号线可以连接在第三和第四通孔之间。第三个信号线可以连接在第五和第六个通孔之间。第一通孔可以在空间上与第五通孔相邻，使得第三信号线上的信号耦合到第一差分信号线，并且第四通孔可以在空间上位于第六通孔附近，使得第三信号线上的信号耦合到第二差分信号线。

8. 发明授权

US06691263B2 Interative decoding based on dominant error events 有权
公开(公告)号：US06691263B2
公开(公告)日：2004-02-10
申请号：US09847953
申请日：2001-05-03
申请人： Bane V. Vasic , Jeffrey L. Sonntag , Inkyu Lee
发明人： Bane V. Vasic , Jeffrey L. Sonntag , Inkyu Lee
IPC分类号： H03M1341
CPC分类号： H03M13/2957 , G11B20/10055 , H03M13/6331 , H03M13/6343
摘要： An iterative decoding system for intersymbol interference (ISI) channels has a module for extracting bit reliabilities from a partial response (PR) channel, an iterative decoder, and a module for updating the bit reliabilities. A transmitter parses a data sequence into blocks that are encoded to generate a sequence of codewords. By encoding, a correlation among the bits of each codeword output to the PR channel is created. A maximum likelihood sequence detector (MLSD) in the receiver produces estimates of transmitted bits from samples of the output from the PR channel. The MLSD detector has a priori knowledge of typical error events that can occur during transmission through the channel. Along with the bit estimates, at each time instant the MLSD detector generates set of error event likelihoods. These error event likelihoods are then converted into bit reliabilities that, together with estimates for the transmitted bits, are used to recalculate the bit reliabilities using the knowledge of the relation between bits within a codeword. The iterative decoder uses this soft input information (bit reliabilities and bit estimates) for each iteration of decoding to improve i) the estimate of the bit reliabilities, ii) the decisions of what bit has been transmitted, and iii) calculations for the error event likelihoods for the next iteration. These error event likelihoods are then converted into bit reliabilities that, together with estimates for the transmitted bits, are used by the iterative decoder to recalculate the bit reliabilities using the knowledge of correlation among bits within the codeword. The error event likelihoods may be updated using the updated bit reliabilities, and the updated error event likelihoods are then converted to new bit reliabilities for the next iteration. In an iterative manner, increasing those bit reliabilities that tend to show increasing confidence for corresponding decoded bits (i.e., corresponding Viterbi decisions) between iterations, while decreasing those reliabilities that tend to show decreasing confidence for corresponding decoded bits, tends to drive the iterative decoding scheme to fewer iterations while maintaining a predetermined probability of error.

9. 发明授权

US5377231A Automatic gain control circuit for a digital baseband line equalizer 失效
标题翻译：用于数字基带线均衡器的自动增益控制电路
公开(公告)号：US5377231A
公开(公告)日：1994-12-27
申请号：US159402
申请日：1993-11-30
申请人： Jeffrey L. Sonntag
发明人： Jeffrey L. Sonntag
IPC分类号： H03G3/20 , H04B3/04 , H04B3/06 , H04M3/40 , H04L27/08
CPC分类号： H04M3/40 , H04B3/04
摘要： An automatic gain control circuit produces a control voltage for a digital baseband line equalizer having a ternary output signal. The circuit includes a capacitor for storing a charge to produce the control voltage, a charge circuit for charging the capacitor if the amplitude of the ternary output signal exceeds a reference voltage, and a discharging circuit for discharging the capacitor only when the ternary output signal is at a non-zero level.
摘要翻译：自动增益控制电路产生具有三进制输出信号的数字基带线均衡器的控制电压。电路包括用于存储产生控制电压的电荷的电容器，如果三元输出信号的幅度超过参考电压，则对电容器充电的充电电路，以及仅当三元输出信号为处于非零级。

10. 发明授权

US07999523B1 Driver with improved power supply rejection 有权
标题翻译：驱动器具有改进的电源抑制
公开(公告)号：US07999523B1
公开(公告)日：2011-08-16
申请号：US12201070
申请日：2008-08-29
申请人： Aaron J. Caffee , Jeffrey L. Sonntag
发明人： Aaron J. Caffee , Jeffrey L. Sonntag
IPC分类号： G05F1/10 , G05F1/44
CPC分类号： H03K19/00361 , H03K3/356104
摘要： A technique reduces effects of power supply noise on a signal output by an integrated circuit output driver circuit powered at least partially by an external power supply. An integrated circuit includes a first circuit that provides a first version of a signal to be output referenced between a first regulated voltage and a first power supply voltage of an external power supply. A second circuit provides a second version of the signal to be output referenced between a second regulated voltage and a second power supply voltage of the external power supply. A third circuit provides a third version of the signal to be output referenced between the first power supply voltage and the second power supply voltage and based on the first and second versions of the signal to be output and power received from the external power supply.
摘要翻译：一种技术减少了由至少部分由外部电源供电的集成电路输出驱动器电路对电源噪声对信号输出的影响。集成电路包括第一电路，其提供在外部电源的第一调节电压和第一电源电压之间参考的要输出的信号的第一版本。第二电路提供要在外部电源的第二调节电压和第二电源电压之间参考的待输出信号的第二版本。第三电路提供在第一电源电压和第二电源电压之间的输出信号的第三版本，并且基于待输出的信号的第一和第二版本以及从外部电源接收的功率。

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