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1. 发明授权

US06040230A Method of forming a nano-rugged silicon-containing layer 失效
标题翻译：形成纳米坚固的含硅层的方法
公开(公告)号：US06040230A
公开(公告)日：2000-03-21
申请号：US39075
申请日：1998-03-13
申请人： John Mark Anthony , Robert M. Wallace , Yi Wei , Glen Wilk
发明人： John Mark Anthony , Robert M. Wallace , Yi Wei , Glen Wilk
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/82
摘要： An embodiment of the instant invention is a method of forming a nano-rugged silicon-containing layer, the method comprising the steps of: providing a first silicon-containing layer (steps 202 or 802); providing a patterning layer over the first silicon-containing layer (steps 204 or 804); the patterning layer comprised of an amorphous substance; providing a second silicon-containing layer (steps 206 or 808) over the patterning layer; and wherein the patterning layer creates a nano-rugged texture in the second silicon-containing layer. Preferably, the first and second silicon-containing layers are comprised of polycrystalline silicon. In an alternative embodiment, the patterning layer is comprised of a material which has small holes such that the step of providing the second silicon-containing layer utilizes the first silicon-containing layer as a seed layer through the small holes so as to form the second silicon-containing layer. In another alternative embodiment, the second silicon-containing layer is comprised of a plurality of islands of the silicon-containing material separated by voids in the material. Preferably, the patterning layer is comprised of SiO.sub.2.
摘要翻译：本发明的一个实施方案是一种形成纳米坚固的含硅层的方法，所述方法包括以下步骤：提供第一含硅层（步骤202或802）; 在第一含硅层上提供图形层（步骤204或804）; 所述图案层由无定形物质构成; 在所述图案化层上提供第二含硅层（步骤206或808）; 并且其中所述图案化层在所述第二含硅层中产生纳米坚固纹理。优选地，第一和第二含硅层由多晶硅组成。在替代实施例中，图案化层由具有小孔的材料构成，使得提供第二含硅层的步骤通过该小孔利用第一含硅层作为种子层，从而形成第二含硅层含硅层。在另一个替代实施例中，第二含硅层由多个岛状的含硅材料构成，该岛由材料中的空隙分开。优选地，图案化层由SiO 2组成。

2. 发明授权

US06613698B2 Lower temperature method for forming high quality silicon-nitrogen dielectrics 有权
公开(公告)号：US06613698B2
公开(公告)日：2003-09-02
申请号：US09859907
申请日：2001-05-17
申请人： Glen D. Wilk , John Mark Anthony , Yi Wei , Robert M. Wallace
发明人： Glen D. Wilk , John Mark Anthony , Yi Wei , Robert M. Wallace
IPC分类号： H01L21318
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3185 , H01L29/511 , H01L29/513 , H01L29/518
摘要： A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.

3. 发明授权

US06274510B1 Lower temperature method for forming high quality silicon-nitrogen dielectrics 有权
标题翻译：用于形成高质量硅 - 氮电介质的较低温度方法
公开(公告)号：US06274510B1
公开(公告)日：2001-08-14
申请号：US09149427
申请日：1998-09-08
申请人： Glen D. Wilk , John Mark Anthony , Yi Wei , Robert M. Wallace
发明人： Glen D. Wilk , John Mark Anthony , Yi Wei , Robert M. Wallace
IPC分类号： H01L21318
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3185 , H01L29/511 , H01L29/513 , H01L29/518
摘要： A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.
摘要翻译：公开了一种在半导体衬底上形成热氮化硅的方法。该方法允许形成足够厚的用于FET栅极电介质但具有低热量预算的热氮化硅。

4. 发明授权

US06730977B2 Lower temperature method for forming high quality silicon-nitrogen dielectrics 有权
标题翻译：用于形成高质量硅 - 氮电介质的较低温度方法
公开(公告)号：US06730977B2
公开(公告)日：2004-05-04
申请号：US10452999
申请日：2003-06-03
申请人： Glen D. Wilk , John Mark Anthony , Yi Wei , Robert M. Wallace
发明人： Glen D. Wilk , John Mark Anthony , Yi Wei , Robert M. Wallace
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3185 , H01L29/511 , H01L29/513 , H01L29/518
摘要： A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.
摘要翻译：公开了一种在半导体衬底上形成热氮化硅的方法。该方法允许形成足够厚的用于FET栅极电介质但具有低热量预算的热氮化硅。

5. 发明授权

US07115461B2 High permittivity silicate gate dielectric 有权
标题翻译：高介电常数硅酸盐栅极电介质
公开(公告)号：US07115461B2
公开(公告)日：2006-10-03
申请号：US11015604
申请日：2004-12-17
申请人： John Mark Anthony , Scott R. Summerfelt , Robert M. Wallace , Glen D. Wilk
发明人： John Mark Anthony , Scott R. Summerfelt , Robert M. Wallace , Glen D. Wilk
IPC分类号： H01L21/8238
CPC分类号： H01L21/31691 , H01L21/02181 , H01L21/02323 , H01L21/0234 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/3143 , H01L21/31612 , H01L21/31641 , H01L21/31645 , H01L29/517
摘要： A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.
摘要翻译：本文公开了包括高介电常数硅酸盐栅极电介质的场效应半导体器件及其形成方法。该器件包括其中形成有半导体沟道区24的硅衬底20。在该衬底上形成金属硅酸盐栅极电介质层36，之后是导电栅极38。硅酸盐层36可以是例如硅酸铪，使得栅极电介质的介电常数显着高于二氧化硅的介电常数。然而，硅酸盐栅极电介质也可以被设计成具有二氧化硅的优点。高击穿，低界面状态密度和高稳定性。本发明包括沉积无定形和多晶硅酸盐层以及梯度组合硅酸盐层的方法。

6. 发明授权

US06841439B1 High permittivity silicate gate dielectric 失效
标题翻译：高介电常数硅酸盐栅极电介质
公开(公告)号：US06841439B1
公开(公告)日：2005-01-11
申请号：US09116138
申请日：1998-07-15
申请人： John Mark Anthony , Scott R. Summerfelt , Robert M. Wallace , Glen D. Wilk
发明人： John Mark Anthony , Scott R. Summerfelt , Robert M. Wallace , Glen D. Wilk
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L29/51 , H01L21/8238
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/3143 , H01L21/31612 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517
摘要： A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.
摘要翻译：本文公开了包括高介电常数硅酸盐栅极电介质的场效应半导体器件及其形成方法。该器件包括其中形成有半导体沟道区24的硅衬底20。在该衬底上形成金属硅酸盐栅极电介质层36，之后是导电栅极38.硅酸盐层36可以是例如硅酸铪，使得栅极电介质的介电常数显着高于二氧化硅的介电常数。然而，硅酸盐栅极电介质也可以被设计成具有二氧化硅的优点。高击穿，低界面状态密度和高稳定性。本发明包括沉积无定形和多晶硅酸盐层以及梯度组合硅酸盐层的方法。

7. 发明申请

US20150329957A1 DEPOSITION AND PATTERNING USING EMITTED ELECTRONS 有权
标题翻译：使用发射电子的沉积和图案
公开(公告)号：US20150329957A1
公开(公告)日：2015-11-19
申请号：US14713366
申请日：2015-05-15
申请人： John Mark Anthony
发明人： John Mark Anthony
IPC分类号： C23C14/22 , C23C14/04
CPC分类号： C23C14/221 , C23C14/04 , C23C14/048
摘要： A method of creating a localized deposition on a sample in a vacuum chamber having an ion source generating a positively-charged beam of ions and a separate source of primary radiation generating a beam of radiation. An ion beam from the ion source is directed toward the sample, and the primary radiation beam is applied to the sample to generate emitted electrons from the sample. The ion beam and the primary radiation beam are positioned so that the paths of at least some of the ions in the ion beam and the paths of at least some of the emitted electrons from the sample substantially overlap in space near the sample surface. The energy of the ions in the ion beam and the electric potential of the sample are adjusted to substantially prevent deposition of ions on the sample. The energy of the ions in the ion beam and the electric potential of the sample are adjusted so that a portion of the ions in the ion beam are neutralized by the emitted electrons from the sample, and such neutralized ions continue in their respective paths to deposit on the sample.
摘要翻译：在具有产生正电荷离子束的离子源和产生辐射束的单独的一次辐射源的真空室中在样品上产生局部沉积的方法。来自离子源的离子束被引向样品，并且将主辐射束施加到样品以从样品产生发射的电子。离子束和主辐射束被定位成使得离子束中的至少一些离子的路径和来自样品的至少一些发射电子的路径在样品表面附近的空间中基本上重叠。离子束中的离子的能量和样品的电位被调节以基本上防止离子沉积在样品上。调整离子束中的离子的能量和样品的电位，使得离子束中的一部分离子被来自样品的发射电子中和，并且这样中和的离子在它们各自的路径中继续沉积在样品上。

8. 发明授权

US06462931B1 High-dielectric constant capacitor and memory 失效
标题翻译：高介电常数电容和存储器
公开(公告)号：US06462931B1
公开(公告)日：2002-10-08
申请号：US08956407
申请日：1997-10-23
申请人： Shaoping Tang , John Mark Anthony , Scott Summerfelt
发明人： Shaoping Tang , John Mark Anthony , Scott Summerfelt
IPC分类号： H01G4008
CPC分类号： H01L27/11502 , H01L27/10814 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： A capacitor (100) with a high dielectric constant oxide dielectric (102) plus Ir- or Ir and Rh bond over the oxygen site in Barium strontium titanate (BST) dielectric to achieve the high Schottky barrier, and very thin layers of Ir or Rh with conductive oxide backing layers (106, 116) provide oxygen depletion deterrence. Rh-containing capacitor plates (104, 114) yielding high Schottky barrier interfaces.
摘要翻译：具有高介电常数氧化物电介质（102）的电容器（102）加上在锶钛酸锶（BST）电介质中的氧位置上的Ir或Ir和Rh键，以实现高肖特基势垒，以及非常薄的Ir或Rh 具有导电氧化物背衬层（106,116）提供氧耗尽威慑。含Rh的电容器板（104,114）产生高肖特基势垒界面。

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