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1. 发明授权

US07115461B2 High permittivity silicate gate dielectric 有权
标题翻译：高介电常数硅酸盐栅极电介质
公开(公告)号：US07115461B2
公开(公告)日：2006-10-03
申请号：US11015604
申请日：2004-12-17
申请人： John Mark Anthony , Scott R. Summerfelt , Robert M. Wallace , Glen D. Wilk
发明人： John Mark Anthony , Scott R. Summerfelt , Robert M. Wallace , Glen D. Wilk
IPC分类号： H01L21/8238
CPC分类号： H01L21/31691 , H01L21/02181 , H01L21/02323 , H01L21/0234 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/3143 , H01L21/31612 , H01L21/31641 , H01L21/31645 , H01L29/517
摘要： A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.
摘要翻译：本文公开了包括高介电常数硅酸盐栅极电介质的场效应半导体器件及其形成方法。该器件包括其中形成有半导体沟道区24的硅衬底20。在该衬底上形成金属硅酸盐栅极电介质层36，之后是导电栅极38。硅酸盐层36可以是例如硅酸铪，使得栅极电介质的介电常数显着高于二氧化硅的介电常数。然而，硅酸盐栅极电介质也可以被设计成具有二氧化硅的优点。高击穿，低界面状态密度和高稳定性。本发明包括沉积无定形和多晶硅酸盐层以及梯度组合硅酸盐层的方法。

2. 发明授权

US06841439B1 High permittivity silicate gate dielectric 失效
标题翻译：高介电常数硅酸盐栅极电介质
公开(公告)号：US06841439B1
公开(公告)日：2005-01-11
申请号：US09116138
申请日：1998-07-15
申请人： John Mark Anthony , Scott R. Summerfelt , Robert M. Wallace , Glen D. Wilk
发明人： John Mark Anthony , Scott R. Summerfelt , Robert M. Wallace , Glen D. Wilk
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L29/51 , H01L21/8238
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/3143 , H01L21/31612 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517
摘要： A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.
摘要翻译：本文公开了包括高介电常数硅酸盐栅极电介质的场效应半导体器件及其形成方法。该器件包括其中形成有半导体沟道区24的硅衬底20。在该衬底上形成金属硅酸盐栅极电介质层36，之后是导电栅极38.硅酸盐层36可以是例如硅酸铪，使得栅极电介质的介电常数显着高于二氧化硅的介电常数。然而，硅酸盐栅极电介质也可以被设计成具有二氧化硅的优点。高击穿，低界面状态密度和高稳定性。本发明包括沉积无定形和多晶硅酸盐层以及梯度组合硅酸盐层的方法。

3. 发明授权

US06291282B1 Method of forming dual metal gate structures or CMOS devices 有权
标题翻译：形成双金属栅极结构或CMOS器件的方法
公开(公告)号：US06291282B1
公开(公告)日：2001-09-18
申请号：US09500330
申请日：2000-02-08
申请人： Glen D. Wilk , Scott R. Summerfelt
发明人： Glen D. Wilk , Scott R. Summerfelt
IPC分类号： H01L218283
CPC分类号： H01L29/4966 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L29/42376 , H01L29/495 , H01L29/66545 , H01L29/6659
摘要： An embodiment of the instant invention is a method of forming a first transistor having a first gate electrode and a second transistor having a second gate electrode on a semiconductor substrate, the method comprising the steps of: forming a conductive material (step 216 of FIG. 2) insulatively disposed over the semiconductor substrate, the conductive material having a work function; and altering a portion of the conductive material (step 218 of FIG. 2) so as to change the work function of the altered conductive material, the conductive material to form the first gate electrode and the altered conductive material to form the second gate electrode. Preferably, the first transistor is an NMOS device, the second transistor is a PMOS device, and the first transistor and the second transistor form a CMOS device. The conductive material is, preferably, comprised of a conductor selected from the group consisting of: Ta, Mo, Ti and any combination thereof. Preferably, the step of altering a portion of the conductive material is comprised of: subjecting the portion of the conductive material to a plasma which incorporates a nitrogen-containing gas.
摘要翻译：本发明的一个实施例是一种在半导体衬底上形成具有第一栅电极和第二晶体管的第一晶体管的方法，所述第一晶体管具有第二栅电极，所述方法包括以下步骤：形成导电材料（图1的步骤216）。 2）绝缘地设置在半导体衬底上，导电材料具有功函数; 并改变导电材料的一部分（图2的步骤218），以改变改变的导电材料的功函数，导电材料形成第一栅电极和改变的导电材料以形成第二栅电极。优选地，第一晶体管是NMOS器件，第二晶体管是PMOS器件，并且第一晶体管和第二晶体管形成CMOS器件。导电材料优选由选自Ta，Mo，Ti及其任何组合的导体组成。优选地，改变导电材料的一部分的步骤包括：使导电材料的该部分经受含有含氮气体的等离子体。

4. 发明授权

US08779485B2 Hydrogen barrier for ferroelectric capacitors 有权
公开(公告)号：US08779485B2
公开(公告)日：2014-07-15
申请号：US13480044
申请日：2012-05-24
申请人： Kezhakkedath R. Udayakumar , Scott R. Summerfelt , Ted S. Moise , Manoj K. Jain
发明人： Kezhakkedath R. Udayakumar , Scott R. Summerfelt , Ted S. Moise , Manoj K. Jain
IPC分类号： H01L21/02 , H01L23/48 , H01L21/768 , H01L49/02 , H01L27/115
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

5. 发明授权

US08416598B2 Differential plate line screen test for ferroelectric latch circuits 有权
公开(公告)号：US08416598B2
公开(公告)日：2013-04-09
申请号：US12781601
申请日：2010-05-17
申请人： Scott R. Summerfelt , John Anthony Rodriguez , Hugh P. McAdams , Steven Craig Bartling
发明人： Scott R. Summerfelt , John Anthony Rodriguez , Hugh P. McAdams , Steven Craig Bartling
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

6. 发明申请

US20120307545A1 Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories 审中-公开
标题翻译： 2T2C铁电存储器的交错位线架构
公开(公告)号：US20120307545A1
公开(公告)日：2012-12-06
申请号：US13150885
申请日：2011-06-01
申请人： Hugh P. McAdams , Scott R. Summerfelt , Patrick M. Ndai
发明人： Hugh P. McAdams , Scott R. Summerfelt , Patrick M. Ndai
IPC分类号： G11C11/22
CPC分类号： G11C11/221
摘要： A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell is physically located between the first and second portions of the first memory cell. As a result, complementary bit lines for adjacent columns are interleaved with one another. Each sense amplifier is associated with a multiplexer, so that the adjacent columns of the interleaved memory cells are supported by a single sense amplifier. Noise coupling among the bit lines is reduced, and the sense amplifiers can be placed along one side of the array, reducing the number of dummy cells required to eliminate edge cell effects.
摘要翻译：具有双晶体管，双电容器（2T2C）型的交错成对的铁电存储器单元的铁电存储器。给定对中的每个存储单元被构造为第一和第二部分，每个部分包括晶体管和铁电电容器。在每对内，第二存储单元的第一部分物理地位于第一存储单元的第一和第二部分之间。结果，用于相邻列的互补位线彼此交错。每个读出放大器与复用器相关联，使得交错存储器单元的相邻列由单个读出放大器支持。位线之间的噪声耦合减少，并且读出放大器可以沿着阵列的一侧放置，减少了消除边缘单元效应所需的虚拟单元的数量。

7. 发明授权

US08324742B2 Alignment mark for opaque layer 有权
标题翻译：不透明层的对齐标记
公开(公告)号：US08324742B2
公开(公告)日：2012-12-04
申请号：US12185003
申请日：2008-08-01
申请人： Scott R. Summerfelt , Stephen A. Meisner , John B. Robbins
发明人： Scott R. Summerfelt , Stephen A. Meisner , John B. Robbins
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.
摘要翻译：公开了在不透明层下使用的接触金属层中的IC对准标记和用于形成对准标记的工艺。对准标记包括几微米宽的接触金属场，在接触蚀刻期间形成的PMD柱阵列，接触金属沉积和选择性接触金属去除过程。柱子被排列成使得接触金属的所有暴露表面是平面的。一个配置是矩形阵列，其中每隔一行被横向偏移列间距的一半。选择柱的水平尺寸以使接触金属填充因子最大化，同时在处理期间向下面的基底提供足够的粘附。作为接触金属去除过程的结果，接触金属比围绕对准标记的PMD层低至少15纳米。

8. 发明授权

US08093070B2 Method for leakage reduction in fabrication of high-density FRAM arrays 有权
标题翻译：高密度FRAM阵列制造中泄漏减少的方法
公开(公告)号：US08093070B2
公开(公告)日：2012-01-10
申请号：US11706722
申请日：2007-02-15
申请人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
发明人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L21/00
CPC分类号： H01L28/75 , H01L27/11507 , H01L28/55
摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
摘要翻译：提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用第二次灰化过程。

9. 发明授权

US08071430B2 Stress buffer layer for ferroelectric random access memory 有权
标题翻译：用于铁电随机存取存储器的应力缓冲层
公开(公告)号：US08071430B2
公开(公告)日：2011-12-06
申请号：US12975098
申请日：2011-01-14
申请人： Scott R. Summerfelt , Kezhakkedath R. Udayakumar , John P. Campbell , Hugh P. McAdams
发明人： Scott R. Summerfelt , Kezhakkedath R. Udayakumar , John P. Campbell , Hugh P. McAdams
IPC分类号： H01L21/56
CPC分类号： H01L23/3135 , H01L23/562 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.
摘要翻译：一种具有包含F-RAM电路的半导体管芯，模具化合物和至少部分地位于半导体管芯和模具化合物之间的应力缓冲层的F-RAM封装。此外，制造F-RAM封装的方法包括提供包含F-RAM电路的半导体管芯，在半导体管芯上形成图案化的应力缓冲层，以及形成耦合到应力缓冲层的模具化合物。

10. 发明申请

US20110079884A1 Hydrogen Passivation of Integrated Circuits 有权
标题翻译：集成电路的氢钝化
公开(公告)号：US20110079884A1
公开(公告)日：2011-04-07
申请号：US12890137
申请日：2010-09-24
申请人： Gul B. Basim , Scott R. Summerfelt , Ted S. Moise
发明人： Gul B. Basim , Scott R. Summerfelt , Ted S. Moise
IPC分类号： H01L29/06 , H01L21/768 , H01L21/31
CPC分类号： H01L21/3003 , H01L21/0217 , H01L21/02274 , H01L21/76829 , H01L21/76832 , H01L29/6659 , H01L29/7833
摘要： An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.
摘要翻译：具有钝化捕获层的集成电路。具有位于钝化捕获层下面的氢或氘释放层的集成电路。用于形成具有氢或氘释放层的集成电路的方法。用于形成具有钝化捕获层的集成电路的方法。

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