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1. 发明授权

US5960294A Method of fabricating a semiconductor device utilizing polysilicon grains 失效
标题翻译：制造利用多晶硅晶粒的半导体器件的方法
公开(公告)号：US5960294A
公开(公告)日：1999-09-28
申请号：US6126
申请日：1998-01-13
申请人： John K. Zahurak , Scott J. DeBoer , Randhir P.S. Thakur , Mark Fischer
发明人： John K. Zahurak , Scott J. DeBoer , Randhir P.S. Thakur , Mark Fischer
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/84 , H01L28/91
摘要： A method of fabricating capacitors for a dynamic random access memory device reduces double bit failures or shorts in the device. The method includes providing a semiconductor substrate underlying an insulative layer having a plurality of storage cells formed therein electrically connected to the substrate. A first conductive layer of rugged polysilicon, which functions as a first capacitor plate, is formed over the insulative layer in an oxygen-free atmosphere such that the first conductive layer is without natural oxides on the surface thereof. The surface of the first conductive layer in the oxygen-free atmosphere is then conditioned by a rapid thermal nitridization process which forms a silicon nitride film thereon. Thereafter, portions of the first conductive layer are removed from the insulative layer such that the plurality of storage cells are electrically isolated from one another. A dielectric layer is then formed over the first conductive layer and exposed insulative layer, followed by a second conductive layer, functioning as a second capacitor plate, being formed over the dielectric layer to complete the capacitor structure.
摘要翻译：一种制造用于动态随机存取存储器件的电容器的方法减少了器件中的双位故障或短路。该方法包括在其上形成有电连接到基板的多个存储单元的绝缘层下方提供半导体基板。在无氧气氛中的绝缘层上形成用作第一电容器板的凹凸多晶硅的第一导电层，使得第一导电层在其表面上不具有天然氧化物。然后在无氧气氛中的第一导电层的表面通过在其上形成氮化硅膜的快速热氮化工艺进行调理。此后，将第一导电层的部分从绝缘层移除，使得多个存储单元彼此电隔离。然后在第一导电层和暴露的绝缘层上形成电介质层，然后在电介质层上形成用作第二电容器板的第二导电层，以完成电容器结构。

2. 发明授权

US6015743A Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon and a hemispherical grain polysilicon layer produced according to the method 失效
标题翻译：提供根据该方法制造的半球形晶粒多晶硅的导电掺杂层和半球状晶粒多晶硅层的半导体加工方法
公开(公告)号：US6015743A
公开(公告)日：2000-01-18
申请号：US64631
申请日：1998-04-22
申请人： John K. Zahurak , Klaus F. Schuegraf , Randhir P.S. Thakur
发明人： John K. Zahurak , Klaus F. Schuegraf , Randhir P.S. Thakur
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/84 , Y10S148/138
摘要： A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate includes, a) providing a layer of conductively doped silicon over the substrate to a thickness greater than about 200 Angstroms; b) depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; c) positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; d) with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; e) with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; f) with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and g) annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350.degree. C. to about 600.degree. C. and at an annealing pressure of from about 10.sup.-4 Torr to about 80 Torr to in situ both diffuse conductivity enhancing impurity into the non-polycrystalline silicon layer and transform the non-polycrystalline silicon layer into a conductively doped hemispherical grain polysilicon layer.
摘要翻译：在衬底上提供半球形晶粒多晶硅的导电掺杂层的半导体处理方法包括：a）在衬底上提供厚度大于约200埃的导电掺杂硅层; b）在掺杂硅层上沉积未掺杂的非多晶硅层至厚度为100埃至约400埃; c）将衬底与掺杂的硅和未掺杂的非多晶硅层定位在化学气相沉积反应器内; d）与其中的基底，将化学气相沉积反应器内的压力降低到等于或低于约200mTorr的第一压力; e）与其中的基板，从第一压力升高化学气相沉积反应器内的压力并用净化气体冲洗反应器; f）其中衬底在其中停止清洗气体的流动并且将化学气相沉积反应器内的压力降低至等于或低于约200mTorr的第二压力; 以及g）在约350℃至约600℃的退火温度和约10℃的退火温度下，在导电性增强杂质气体存在下退火具有沉积的非多晶硅层的衬底， 4乇至约80乇原位扩散导电性增强杂质进入非多晶硅层，并将非多晶硅层转变为导电掺杂半球形晶粒多晶硅层。

3. 发明授权

US5989973A Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon and a hemispherical grain polysilicon layer produced according to the method 失效
标题翻译：提供根据该方法制造的半球形晶粒多晶硅的导电掺杂层和半球状晶粒多晶硅层的半导体加工方法
公开(公告)号：US5989973A
公开(公告)日：1999-11-23
申请号：US820712
申请日：1997-03-18
申请人： John K. Zahurak , Klaus F. Schuegraf , Randhir P.S. Thakur
发明人： John K. Zahurak , Klaus F. Schuegraf , Randhir P.S. Thakur
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/84 , Y10S148/138
摘要： A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate includes, a) providing a layer of conductively doped silicon over the substrate to a thickness greater than about 200 Angstroms; b) depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; c) positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; d) with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; e) with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; f) with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and g) annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350.degree. C. to about 600.degree. C. and at an annealing pressure of from about 10.sup.4 Torr to about 80 Torr to in situ both diffuse conductivity enhancing impurity into the non-polycrystalline silicon layer and transform the non-polycrystalline silicon layer into a conductively doped hemispherical grain polysilicon layer.
摘要翻译：在衬底上提供半球形晶粒多晶硅的导电掺杂层的半导体处理方法包括：a）在衬底上提供厚度大于约200埃的导电掺杂硅层; b）在掺杂硅层上沉积未掺杂的非多晶硅层至厚度为100埃至约400埃; c）将衬底与掺杂的硅和未掺杂的非多晶硅层定位在化学气相沉积反应器内; d）与其中的基底，将化学气相沉积反应器内的压力降低到等于或低于约200mTorr的第一压力; e）与其中的基板，从第一压力升高化学气相沉积反应器内的压力并用净化气体冲洗反应器; f）其中衬底在其中停止清洗气体的流动并且将化学气相沉积反应器内的压力降低至等于或低于约200mTorr的第二压力; 并且g）在退火温度为约350℃至约600℃，退火温度为约104托的条件下，在导电性增强杂质气体存在下使具有沉积的非多晶硅层的基板退火至约80托，原位将扩散导电性增强杂质进入非多晶硅层，并将非多晶硅层转化为导电掺杂的半球状晶粒多晶硅层。

4. 发明申请

US20090152247A1 Fast axis beam profile shaping for high power laser diode based annealing system 有权
标题翻译：基于高功率激光二极管的退火系统的快轴光束轮廓成形
公开(公告)号：US20090152247A1
公开(公告)日：2009-06-18
申请号：US12291002
申请日：2008-11-04
申请人： Dean Jennings , Abhilash J. Mayur , Timothy N. Thomas , Vijay Parihar , Vedapuram S. Achutharaman , Randhir P.S. Thakur
发明人： Dean Jennings , Abhilash J. Mayur , Timothy N. Thomas , Vijay Parihar , Vedapuram S. Achutharaman , Randhir P.S. Thakur
IPC分类号： B23K26/00
CPC分类号： B23K26/0738 , B23K26/0613 , B23K26/0676 , H01L21/268 , H01L29/7833 , Y10T117/1016
摘要： A dynamic surface anneal apparatus for annealing a semiconductor workpiece has a workpiece support for supporting a workpiece, an optical source and scanning apparatus for scanning the optical source and the workpiece support relative to one another along a fast axis. The optical source includes an array of laser emitters arranged generally in successive rows of the emitters, the rows being transverse to the fast axis. Plural collimating lenslets overlie respective ones of the rows of emitters and provide collimation along the fast axis. The selected lenslets have one or a succession of optical deflection angles corresponding to beam deflections along the fast axis for respective rows of emitters. Optics focus light from the array of laser emitters onto a surface of the workpiece to form a succession of line beams transverse to the fast axis spaced along the fast axis in accordance with the succession of deflection angles.
摘要翻译：用于退火半导体工件的动态表面退火装置具有用于支撑工件的工件支撑件，用于沿着快轴相对于彼此扫描光源和工件支撑件的光源和扫描装置。光源包括大致以发射器的连续行布置的激光发射器的阵列，该列横向于快轴。多个准直的小透镜叠加在发射器排中的相应行上，并沿着快轴提供准直。所选择的小透镜具有对应于沿着快轴的光束偏转的相应行发射器的一个或一系列光学偏转角。将来自激光发射器阵列的光聚焦到工件的表面上，以根据偏转角的顺序形成一系列沿着快轴间隔开的快轴的线束。

5. 发明授权

US07217614B2 Methods to form electronic devices and methods to form a material over a semiconductive substrate 有权
标题翻译：形成电子器件的方法和在半导体衬底上形成材料的方法
公开(公告)号：US07217614B2
公开(公告)日：2007-05-15
申请号：US10338523
申请日：2003-01-07
申请人： Randhir P.S. Thakur
发明人： Randhir P.S. Thakur
IPC分类号： H01L21/8234 , H01L21/8244 , H01L21/31
CPC分类号： H01L21/3145 , C23C16/345 , H01L21/3144 , H01L21/3185 , H01L27/10852 , H01L28/40
摘要： A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition using feed gases comprising a silicon hydride, H2 and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode.In one implementation, the chemical vapor depositing comprises feed gases of a silicon hydride and ammonia, with the depositing comprising increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. and starting feed of the silicon hydride into the reactor at a temperature less than or equal to 600° C. In one implementation the depositing comprises increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. using a temperature ramp rate of at least 10° C./minute from at least 500° C. to at least 600° C. Other aspects and implementations are described.
摘要翻译：第一电极和其侧向附近的掺杂氧化物层设置在衬底上。通过低压化学气相沉积，使用包含氢化硅H 2的进料气体，在掺杂氧化物层和第一电极之上形成氮化硅层至少在第一电极上不大于80埃的厚度和氨。具有氮化硅层的衬底暴露于包括至少700℃的氧化条件，以在氮化硅层上方形成二氧化硅层，掺杂氧化物层上的氮化硅厚度足以将可氧化的衬底材料屏蔽在掺杂的氧化物层在曝光期间被氧化。在二氧化硅层和第一电极上形成第二电极。在一个实施方案中，化学气相沉积包括氢化硅和氨的进料气体，沉积物包括将内部反应器温度从低于500℃增加至高于600℃的最大沉积温度，并将硅氢化物的原料进料反应器的温度低于或等于600℃。在一个实施方案中，沉积包括使内部反应器温度从低于500℃增加至高于600℃的最大沉积温度，使用至少10°的温度升温速率从至少500℃至至少600℃的/分钟。其他方面和实施方式进行了描述。

6. 发明授权

US6015997A Semiconductor structure having a doped conductive layer 失效
公开(公告)号：US6015997A
公开(公告)日：2000-01-18
申请号：US803174
申请日：1997-02-19
申请人： Yongjun Hu , Pai-Hung Pan , Er-Xuan Ping , Randhir P.S. Thakur , Scott DeBoer
发明人： Yongjun Hu , Pai-Hung Pan , Er-Xuan Ping , Randhir P.S. Thakur , Scott DeBoer
IPC分类号： H01L21/28 , H01L29/49 , H01L29/76 , H01L29/74 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28044 , H01L21/28052 , H01L29/4941
摘要： Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffusion barrier coupled between a polysilicon layer and a conductor layer; a thin nitride layer coupled between a bottom silicon layer and a titanium silicide conductor layer, and a bottom silicon layer coupled to a conductor layer, which comprises C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.

7. 发明申请

US20120208345A1 METHOD FOR FORMING A SELF-ALIGNED ISOLATION STRUCTURE UTILIZING SIDEWALL SPACERS AS AN ETCH MASK AND REMAINING AS A PORTION OF THE ISOLATION STRUCTURE 审中-公开
标题翻译：用于形成隔离隔离层的自对准隔离结构的方法作为隔离层，并且作为隔离结构的一部分
公开(公告)号：US20120208345A1
公开(公告)日：2012-08-16
申请号：US13454187
申请日：2012-04-24
申请人： Fernando Gonzalez , David Chapek , Randhir P.S. Thakur
发明人： Fernando Gonzalez , David Chapek , Randhir P.S. Thakur
IPC分类号： H01L21/762
CPC分类号： H01L21/76237
摘要： The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.
摘要翻译：本发明涉及在半导体衬底中形成微电子结构的方法。该方法包括选择性地去除介电材料以暴露覆盖半导体衬底的氧化物的一部分。绝缘材料可以基本上顺应地形成在电介质材料的氧化物和剩余部分上。间隔物可以由绝缘材料形成。隔离沟蚀刻遵循间隔物蚀刻。可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。可以在绝缘材料的剩余部分上基本上顺应地在间隔物上形成共形材料，并且基本上填充隔离沟槽。保形材料的平面化可能遵循。

8. 发明授权

US08202806B2 Method to avoid threshold voltage shift in thicker dielectric films 失效
标题翻译：避免较厚介质膜中阈值电压漂移的方法
公开(公告)号：US08202806B2
公开(公告)日：2012-06-19
申请号：US11242375
申请日：2005-10-03
申请人： Randhir P.S. Thakur , Ravi Iyer , Howard Rhodes
发明人： Randhir P.S. Thakur , Ravi Iyer , Howard Rhodes
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/3171 , H01L21/02129 , H01L21/02271 , H01L21/02304 , H01L21/02315 , H01L21/31612 , H01L21/3162 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
摘要翻译：提供了一种制造具有降低的阈值电压偏移的集成电路的方法。在半导体衬底上形成非导电区域，在半导体衬底上形成有源区域。有源区由非导电区分开。势垒层和电介质层沉积在非导电区域上并在有源区上方。对集成电路施加热量，导致阻挡层退火。

9. 发明授权

US5869405A In situ rapid thermal etch and rapid thermal oxidation 失效
标题翻译：原位快速热蚀刻和快速热氧化
公开(公告)号：US5869405A
公开(公告)日：1999-02-09
申请号：US582587
申请日：1996-01-03
申请人： Fernando Gonzalez , Randhir P.S. Thakur
发明人： Fernando Gonzalez , Randhir P.S. Thakur
IPC分类号： H01L21/311 , H01L21/316
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02301 , H01L21/31116 , H01L21/31662 , Y10S438/906 , Y10S438/913
摘要： At least both a rapid thermal etch step and a rapid thermal oxidation step are performed on a semiconductor substrate in situ in a rapid thermal processor. A method including an oxidation step followed by an etch step may be used to remove contamination and damage from a substrate. A method including a first etch step followed by an oxidation step and a second etch step may likewise be used to remove contamination and damage, and a final oxidation step may optionally be included to grow an oxide film. A method including an etch step followed by an oxidation step may also be used to grow an oxide film. Repeated alternate in situ oxidation and etch steps may be used until a desired removal of contamination or silicon damage is accomplished.
摘要翻译：在快速热处理器中至少在半导体衬底上进行快速热蚀刻步骤和快速热氧化步骤。可以使用包括氧化步骤和随后的蚀刻步骤的方法来去除基底的污染和损伤。同样可以使用包括第一蚀刻步骤之后的氧化步骤和第二蚀刻步骤的方法来去除污染物和损伤，并且可以任选地包括最终氧化步骤以生长氧化膜。包括氧化步骤之后的蚀刻步骤的方法也可用于生长氧化膜。可以使用重复的原位氧化和蚀刻步骤，直到完成所需的污染物或硅损伤去除。

10. 发明申请

US20100273309A1 METHOD FOR FORMING A SELF ALIGNED ISOLATION TRENCH 有权
标题翻译：形成自对准隔离层的方法
公开(公告)号：US20100273309A1
公开(公告)日：2010-10-28
申请号：US12828868
申请日：2010-07-01
申请人： Fernando Gonzalez , David Chapek , Randhir P.S. Thakur
发明人： Fernando Gonzalez , David Chapek , Randhir P.S. Thakur
IPC分类号： H01L21/762
CPC分类号： H01L21/76237
摘要： The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.
摘要翻译：本发明涉及在半导体衬底中形成微电子结构的方法。该方法包括选择性地去除介电材料以暴露覆盖半导体衬底的氧化物的一部分。绝缘材料可以基本上顺应地形成在电介质材料的氧化物和剩余部分上。间隔物可以由绝缘材料形成。隔离沟蚀刻遵循间隔物蚀刻。可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。可以在绝缘材料的剩余部分上基本上顺应地在间隔物上形成共形材料，并且基本上填充隔离沟槽。保形材料的平面化可能遵循。

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