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1. 发明授权

CN1130010C 制造片状电子部件的方法失效
公开(公告)号：CN1130010C
公开(公告)日：2003-12-03
申请号：CN99102259.9
申请日：1999-02-14
申请人：株式会社村田制作所
发明人：宝田益义 , 松本贵宏
IPC分类号： H03H3/02
CPC分类号： H03H9/178 , H01L41/29 , Y10S148/138 , Y10S438/964
摘要：一种制造片状电子部件的方法，包括下述步骤：通过层叠多个基片及括在两个基片之间的至少一个内部电极形成包括主表面和侧面的多层本体，在多层本体的侧面处的两个基片之间形成凹槽，从而露出至少一个内部电极的端部，并且通过对多层本体滚筒抛光，使多层本体的侧面粗糙，在提供了水、媒质、研磨粉和多层本体的滚筒中进行滚筒抛光，并且在多层本体的侧面上形成外部电极，外部电极连接到在凹槽处露出的内部电极的端部。

2. 发明公开

CN1237035A 制造片状电子部件的方法失效
公开(公告)号：CN1237035A
公开(公告)日：1999-12-01
申请号：CN99102259.9
申请日：1999-02-14
申请人：株式会社村田制作所
发明人：宝田益义 , 松本贵宏
IPC分类号： H03H3/02
CPC分类号： H03H9/178 , H01L41/29 , Y10S148/138 , Y10S438/964
摘要：一种制造片状电子部件的方法,包括下述步骤:通过层叠多个基片及括在两个基片之间的至少一个内部电极形成包括主表面和侧面的多层本体,在多层本体的侧面处的两个基片之间形成凹槽,从而露出至少一个内部电极的端部,并且通过对多层本体滚筒抛光,使多层本体的侧面粗糙,在提供了水、媒质、研磨粉和多层本体的滚筒中进行滚筒抛光,并且在多层本体的侧面上形成外部电极,外部电极连接到在凹槽处露出的内部电极的端部。

3. 发明授权

EP0431522B1 Method for manufacturing semiconductor device 失效
标题翻译：一种用于制造半导体器件的工艺。
公开(公告)号：EP0431522B1
公开(公告)日：1995-02-15
申请号：EP90123107.6
申请日：1990-12-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinada, Kazuyoshi, c/o Intellectual Property Div. , Yoshida, Masayuki, c/o Intellectual Property Div. , Mizutani, Takahide, c/o Intellectual Property Div. , Hanada, Naoki, c/o Intellectual Property Division
IPC分类号： H01L21/82
CPC分类号： H01L27/11526 , H01L21/82 , H01L27/115 , H01L27/11539 , Y10S148/138

4. 发明授权

US5885869A Method for uniformly doping hemispherical grain polycrystalline silicon 失效
标题翻译：均匀掺杂半球状晶粒多晶硅的方法
公开(公告)号：US5885869A
公开(公告)日：1999-03-23
申请号：US528183
申请日：1995-09-14
申请人： Charles Turner , Randhir P. S. Thakur
发明人： Charles Turner , Randhir P. S. Thakur
IPC分类号： H01L21/22 , H01L21/02 , H01L21/3215 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/20
CPC分类号： H01L28/84 , H01L21/32155 , H01L27/10808 , H01L29/66181 , Y10S148/014 , Y10S148/122 , Y10S148/138
摘要： A method is disclosed for uniformly doping HSG polycrystalline silicon independent of the other layers of the semiconductor substrate. A semiconductor substrate having a silicon dioxide layer formed superjacent a polysilicon layer is provided in a chamber. A doped rough silicon layer is formed in situ superjacent the silicon dioxide layer. This is accomplished by depositing the silicon layer superjacent the silicon dioxide layer and exposing the silicon layer to a source gas, a dopant gas, and energy, preferably in situ to thereby form uniformly doped silicon layer and roughened polysilicon layer using rapid thermal chemical vapor deposition techniques or low pressure chemical vapor deposition.Alternatively, a uniformly doped roughened polysilicon layer is formed superjacent the silicon dioxide layer in situ. This formation is achieved by depositing an amorphous silicon layer superjacent the silicon dioxide layer and roughening the amorphous silicon layer in situ. The step of roughening is achieved by vacuum annealing the amorphous silicon layer using rapid thermal chemical vapor deposition techniques or low pressure chemical vapor deposition. The roughened amorphous silicon layer is doped by exposing to a source gas, a dopant gas and energy.
摘要翻译：公开了与半导体衬底的其他层无关的均匀掺杂HSG多晶硅的方法。具有在多晶硅层之上形成的二氧化硅层的半导体衬底设置在室中。掺杂的粗硅层原位形成在二氧化硅层的上方。这是通过沉积超过二氧化硅层的硅层并将硅层暴露于源气体，掺杂剂气体和能量，优选在原位，由此形成均匀掺杂的硅层和使用快速热化学气相沉积的粗糙多晶硅层技术或低压化学气相沉积。或者，原位形成在二氧化硅层之上的均匀掺杂的粗糙多晶硅层。通过沉积位于二氧化硅层之上的非晶硅层并原位粗化非晶硅层来实现该形成。通过使用快速热化学气相沉积技术或低压化学气相沉积对非晶硅层进行真空退火来实现粗糙化的步骤。粗糙化的非晶硅层通过暴露于源气体，掺杂剂气体和能量而被掺杂。

5. 发明授权

US5670406A Method of making a tooth shaped capacitor 失效
标题翻译：制造牙形电容器的方法
公开(公告)号：US5670406A
公开(公告)日：1997-09-23
申请号：US791505
申请日：1997-01-30
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/92 , Y10S148/138 , Y10S438/947
摘要： A method of manufacturing a capacitor for use in semiconductor memories is disclosed herein. The present invention includes forming anti-oxidizing regions from dot silicon for use as an oxidation mask to oxidize a polysilicon layer. Further, a silicon oxide layer is used as an etching mask to form a bottom storage node of a capacitor. An etching process is performed to etch a portion of the first polysilicon layer. Next, the silicon oxide layer is removed to define the bottom storage node. Utilizing the bottom storage node structure, the present invention can be used to increase the surface area of the capacitor.
摘要翻译：本文公开了制造用于半导体存储器的电容器的方法。本发明包括从点硅形成抗氧化区域以用作氧化掩模以氧化多晶硅层。此外，使用氧化硅层作为蚀刻掩模来形成电容器的底部存储节点。执行蚀刻工艺以蚀刻第一多晶硅层的一部分。接下来，去除氧化硅层以限定底部存储节点。利用底部存储节点结构，本发明可以用于增加电容器的表面积。

6. 发明授权

US5639685A Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon 失效
标题翻译：提供半导体晶粒多晶硅的导电掺杂层的半导体加工方法
公开(公告)号：US5639685A
公开(公告)日：1997-06-17
申请号：US539851
申请日：1995-10-06
申请人： John K. Zahurak , Klaus F. Schuegraf , Randhir P. S. Thakur
发明人： John K. Zahurak , Klaus F. Schuegraf , Randhir P. S. Thakur
IPC分类号： H01L21/02 , H01L21/70
CPC分类号： H01L28/84 , Y10S148/138
摘要： A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate includes, a) providing a layer of conductively doped silicon over the substrate to a thickness greater than about 200 Angstroms; b) depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; c) positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; d) with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; e) with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; f) with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and g) annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350.degree. C. to about 600.degree. C. and at an annealing pressure of from about 10.sup.-4 Torr to about 80 Torr to in situ both diffuse conductivity enhancing impurity into the non-polycrystalline silicon layer and transform the non-polycrystalline silicon layer into a conductively doped hemispherical grain polysilicon layer.
摘要翻译：在衬底上提供半球形晶粒多晶硅的导电掺杂层的半导体处理方法包括：a）在衬底上提供厚度大于约200埃的导电掺杂硅层; b）在掺杂硅层上沉积未掺杂的非多晶硅层至厚度为100埃至约400埃; c）将衬底与掺杂的硅和未掺杂的非多晶硅层定位在化学气相沉积反应器内; d）与其中的基底，将化学气相沉积反应器内的压力降低到等于或低于约200mTorr的第一压力; e）与其中的基板，从第一压力升高化学气相沉积反应器内的压力并用净化气体冲洗反应器; f）其中衬底在其中停止清洗气体的流动并且将化学气相沉积反应器内的压力降低至等于或低于约200mTorr的第二压力; 以及g）在约350℃至约600℃的退火温度和约10℃的退火温度下，在导电性增强杂质气体存在下退火具有沉积的非多晶硅层的衬底， 4乇至约80乇原位扩散导电性增强杂质进入非多晶硅层，并将非多晶硅层转变为导电掺杂半球形晶粒多晶硅层。

7. 发明授权

US5670405A Method of making a tooth shaped capacitor using ion implantation 失效
标题翻译：使用离子注入制造牙形电容器的方法
公开(公告)号：US5670405A
公开(公告)日：1997-09-23
申请号：US791504
申请日：1997-01-30
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/70
CPC分类号： H01L28/92 , Y10S148/138
摘要： A method of manufacturing a capacitor for use in semiconductor memories is disclosed herein. The present invention includes forming a silicon oxide layer as an etching mask to etch a polysilicon layer to form a bottom storage node of a capacitor. The silicon oxide layer is formed from the thermal annealing of oxygen doped dot silicon.
摘要翻译：本文公开了制造用于半导体存储器的电容器的方法。本发明包括形成氧化硅层作为蚀刻掩模以蚀刻多晶硅层以形成电容器的底部存储节点。氧化硅层由氧掺杂点硅的热退火形成。

8. 发明授权

US5372962A Method of making a semiconductor integrated circuit device having a capacitor with a porous surface of an electrode 失效
标题翻译：制造具有电极多孔表面的电容器的半导体集成电路器件的方法
公开(公告)号：US5372962A
公开(公告)日：1994-12-13
申请号：US11855
申请日：1993-02-01
申请人： Toshiyuki Hirota , Ichirou Honma , Hirohito Watanabe , Masanobu Zenke
发明人： Toshiyuki Hirota , Ichirou Honma , Hirohito Watanabe , Masanobu Zenke
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L27/10808 , Y10S148/138 , Y10S438/964
摘要： A capacitor incorporated in a semiconductor integrated circuit device is expected to have a large amount of capacitance without increase of the occupation area, and has a lower electrode increased in surface area by using a roughening technique selected from the group consisting of an anodizing technique, an anodic oxidation, a wet etching and a dry etching so that a surface of the lower electrode becomes porous, thereby increasing the capacitance.
摘要翻译：期望并入半导体集成电路器件中的电容器具有大量的电容而不增加占用面积，并且通过使用选自以下的粗糙化技术，具有增加表面积的下电极，所述粗糙化技术包括阳极氧化技术，阳极氧化，湿蚀刻和干蚀刻，使得下电极的表面变多孔，从而增加电容。

9. 发明授权

US5094967A Method for manufacturing semiconductor device having a non-volatile memory cell and logic regions by using a CVD second insulating film 失效
标题翻译：使用CVD第二绝缘膜制造具有非易失性存储单元和逻辑区域的半导体器件的方法
公开(公告)号：US5094967A
公开(公告)日：1992-03-10
申请号：US620701
申请日：1990-12-03
申请人： Kazuyoshi Shinada , Masayuki Yoshida , Takahide Mizutani , Naoki Hanada
发明人： Kazuyoshi Shinada , Masayuki Yoshida , Takahide Mizutani , Naoki Hanada
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/82 , H01L27/115 , H01L27/11539 , Y10S148/138
摘要： A method for manufacturing a semiconductor substrate device having a non-volatile memory cell region and a logic region including MOS transistors. A first insulating film and a first electrode layer are formed on a semiconductor substrate. Only those portions of the first insulating film and first electrode layer which are located in the logic region are removed, without removing those portions of the first insulating film and first electrode layer which are located in the non-volatile memory cell region. A sacrificial film is deposited for insulation over the entire surface of the memory cell region and logic region, and then a resist film is coated on the sacrificial film. Subsequently, impurity ions are implanted into a desired channel region located in the logic region. The resist film and sacrificial film are removed, and thereafter a second insulating film and a second electrode layer are formed.

10. 发明专利

JPS60189971A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS60189971A
公开(公告)日：1985-09-27
申请号：JP4521684
申请日：1984-03-09
申请人： Toshiba Corp
发明人： USAMI TOSHIROU , MIKATA YUUICHI , SHINADA KAZUYOSHI
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28273 , Y10S148/053 , Y10S148/138 , Y10S148/169
摘要： PURPOSE: To contrive the improvement in characteristic of withstand voltage of the oxide film on an amorphous single crystal Si film and in leakage characteristic by a method wherein an amorphous single crystal Si film serving as the first gate electrode is deposited on a semiconductor substrate and an insulation film is then formed thereon, through which an impurity is ion-implanted to the amorphous single crystal Si film, and the insulation film is removed; thereafter, the second gate oxide film is formed on the surface of the amorphous single crystal Si film.
CONSTITUTION: A field oxide film 22 is formed on the surface of the P
- type Si substrate 21 having a crystal orientation of (100); thereafter, the first gate oxide film 23 is formed on the surface of the substrate 21 surrounded by the oxide film 22 by heat treatment. Next, the first polycrystalline Si film 24 of no doping is deposited over the entire surface. Phosphorus is ion-implanted to the polycrystalline Si film 24 through a CVD oxide film 25. After annealing in a nitrogen atmosphere, the oxide film 25 is removed. Then, the second gate oxide film 26 is formed on the surface of the polycrystalline Si film 24. The second polycrystalline Si film 27, second gate oxide film 26, first polycrystalline film 24, and first gate oxide film 23 are successively removed by etching.
COPYRIGHT: (C)1985,JPO&Japio
摘要翻译：目的：通过在半导体衬底上沉积作为第一栅电极的非晶单晶Si膜而将半导体衬底上的氧化物膜的耐电压特性提高到非晶单晶硅膜的漏电特性，然后在其上形成绝缘膜，将杂质离子注入到非晶单晶Si膜中，并除去绝缘膜; 此后，在非晶单晶Si膜的表面上形成第二栅氧化膜。构成：在具有（100）晶体取向的P型Si衬底21的表面上形成场氧化膜22。此后，通过热处理在由氧化物膜22包围的基板21的表面上形成第一栅极氧化膜23。接下来，在整个表面上沉积无掺杂的第一多晶Si膜24。通过CVD氧化膜25将磷离子注入到多晶硅膜24中。在氮气气氛中退火后，除去氧化膜25。然后，在多晶硅膜24的表面上形成第二栅极氧化膜26.通过蚀刻，依次除去第二多晶Si膜27，第二栅极氧化膜26，第一多晶膜24和第一栅极氧化膜23。

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