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    • 3. 发明申请
    • SEALING ARRANGEMENT FOR SHAFT AND TUNNEL CONSTRUCTIONS
    • 密封装置和隧道结构
    • US20120328369A1
    • 2012-12-27
    • US13516329
    • 2010-11-29
    • Heiko HoeftHolger GutschmidtAndreas DienerAndreas ArtusMark FischerMatthias Klug
    • Heiko HoeftHolger GutschmidtAndreas DienerAndreas ArtusMark FischerMatthias Klug
    • E21D11/38F16J15/06
    • E21D11/385
    • A sealing arrangement for shaft and tunnel constructions. The sealing of gaps between components of shaft and tunnel constructions is improved, in particular if the components are misaligned. For this purpose a) the sealing arrangement (1) comprises at least two components (2), which lie against each other at butt sides (3) so as to form a gap (4), b) the components (2) have an elastic sealing profile (5) on each butt side (3), and c) the sealing profiles (5) of the butt sides (3) that lie against each other lie against each other on a contact plane (6) and bridge the gap (4) in a sealing manner. The sealing profiles (5) have areas (7, 8) of different hardness arranged in alternation in the transverse direction (9) perpendicular to the respective profile longitudinal plane (10), the sealing profiles (5) of butt sides (3) that lie against each other differing from each other in the arrangement of the areas (7, 8) of different hardness in the transverse direction (9).
    • 轴和隧道结构的密封装置。 改进了轴和组件之间的间隙的密封,特别是如果部件不对准。 为此目的a)密封装置(1)包括至少两个部件(2),它们在对接面(3)处彼此相对以形成间隙(4),b)部件(2)具有 每个对接侧(3)上的弹性密封型材(5),以及c)彼此相对的对接面(3)的密封型材(5)在接触平面(6)上彼此抵靠并桥接间隙 (4)。 密封型材(5)具有垂直于相应轮廓纵向平面(10)的横向(9)交替地布置的具有不同硬度的区域(7,8),对接侧面(3)的密封型材(5) 在横向(9)上具有不同硬度的区域(7,8)的布置彼此不同。
    • 4. 发明申请
    • Methods Of Forming Transistors, And Methods Of Forming Memory Arrays
    • 形成晶体管的方法,以及形成记忆阵列的方法
    • US20120238061A1
    • 2012-09-20
    • US13485892
    • 2012-05-31
    • Mark FischerSanh D. Tang
    • Mark FischerSanh D. Tang
    • H01L21/336
    • H01L27/10876H01L21/823425H01L21/823487H01L27/2454H01L29/0653H01L29/42368H01L29/456H01L29/66666H01L29/7827H01L45/06H01L45/1233
    • Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.
    • 一些实施例包括形成垂直晶体管的方法。 结构可以具有从半导体衬底向上延伸的多个间隔开的翅片。 每个鳍片可以具有垂直的晶体管柱,并且每个垂直晶体管柱可以具有底部源极/漏极区域位置,在底部源极/漏极区域位置上方的沟道区域位置,以及顶部源极/漏极区域 渠道区域位置。 导电栅极材料可以沿着鳍片形成,同时沿着鳍状物的底部在空间内使用氧化物以将导电栅极材料偏移到垂直晶体管柱的底部源极/漏极区域的上方。 氧化物可以是在室温下用稀释HF以至少约100埃/分钟的速率蚀刻的氧化物。 在一些实施例中,可以在形成导电栅极材料之后去除氧化物。
    • 5. 发明授权
    • Processes and apparatus having a semiconductor fin
    • 具有半导体散热片的方法和装置
    • US08154081B2
    • 2012-04-10
    • US13017854
    • 2011-01-31
    • Mark FischerT. Earl AllenH. Montgomery Manning
    • Mark FischerT. Earl AllenH. Montgomery Manning
    • H01L27/12
    • H01L29/785H01L29/66818H01L29/7853Y10S438/947
    • A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree in the lateral direction than the vertical direction. The process may include second etching the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded hard mask. The thinned semiconductor fin may have a characteristic dimension that can exceed photolithography limits. Electronic devices may include the thinned semiconductor fin as part of a field effect transistor.
    • 工艺可以包括首先通过与散热片半导体的侧壁邻接的电介质硬掩模蚀刻沟槽隔离电介质。 可以执行第一蚀刻以暴露侧壁的至少一部分,使得电介质硬掩模在横向方向上比垂直方向更大程度地退回。 该方法可以包括第二蚀刻鳍式半导体以实现减薄的半导体鳍片,其已经在横向后退的硬掩模的阴影之下退化。 减薄的半导体鳍片可以具有可超过光刻极限的特征尺寸。 电子器件可以包括作为场效应晶体管的一部分的变薄的半导体鳍片。
    • 7. 发明申请
    • Methods Of Forming Pluralities Of Vertical Transistors, And Methods Of Forming Memory Arrays
    • 形成多个垂直晶体管的方法,以及形成记忆阵列的方法
    • US20120052640A1
    • 2012-03-01
    • US12872705
    • 2010-08-31
    • Mark FischerSanh D. Tang
    • Mark FischerSanh D. Tang
    • H01L21/336
    • H01L27/10876H01L21/823425H01L21/823487H01L27/2454H01L29/0653H01L29/42368H01L29/456H01L29/66666H01L29/7827H01L45/06H01L45/1233
    • Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.
    • 一些实施例包括形成垂直晶体管的方法。 结构可以具有从半导体衬底向上延伸的多个间隔开的翅片。 每个鳍片可以具有垂直的晶体管柱,并且每个垂直晶体管柱可以具有底部源极/漏极区域位置,在底部源极/漏极区域位置上方的沟道区域位置,以及顶部源极/漏极区域 渠道区域位置。 导电栅极材料可以沿着鳍片形成,同时沿着鳍状物的底部在空间内使用氧化物以将导电栅极材料偏移到垂直晶体管柱的底部源极/漏极区域的上方。 氧化物可以是在室温下用稀释HF以至少约100埃/分钟的速率蚀刻的氧化物。 在一些实施例中,可以在形成导电栅极材料之后去除氧化物。