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1. 发明授权

US06434076B1 Refresh control circuit for low-power SRAM applications 有权
标题翻译：刷新控制电路，用于低功耗SRAM应用
公开(公告)号：US06434076B1
公开(公告)日：2002-08-13
申请号：US09766799
申请日：2001-01-22
申请人： John E. Andersen , Louis L. Hsu , Stephen Kosonocky , Li-Kong Wang
发明人： John E. Andersen , Louis L. Hsu , Stephen Kosonocky , Li-Kong Wang
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C11/406
摘要： A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to local supplies during an active mode of operation. The power management circuit comprises: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory array refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode. During the low power mode, the refresh circuit intentionally enables the local power supply to float and allow it to drift to a lower predetermined voltage level prior to the memory array refresh operation.
摘要翻译：一种用于SRAM系统的电源管理电路，包括一个或多个隔离存储器阵列，并且在主动操作模式期间实现包括与每个存储器阵列相关联的本地电源的电源和连接到本地电源的外部电源。电源管理电路包括：开关机构，用于在低功率操作模式期间断开外部电源到每个本地电源; 以及通过在低功率模式期间选择性地将外部电源连接到各个本地电源来实现存储器阵列刷新操作的刷新定时电路。在低功率模式期间，刷新电路有意地使本地电源浮动并允许其在存储器阵列刷新操作之前漂移到较低的预定电压电平。

2. 发明申请

US20060049843A1 System and method using locally heated island for integrated circuit testing 失效
标题翻译：使用本地加热岛进行集成电路测试的系统和方法
公开(公告)号：US20060049843A1
公开(公告)日：2006-03-09
申请号：US10936164
申请日：2004-09-08
申请人： Keith Jenkins , Stephen Kosonocky
发明人： Keith Jenkins , Stephen Kosonocky
IPC分类号： G01R31/26
CPC分类号： G01R31/2877 , G01R31/286 , G01R31/3008 , G01R31/31721 , G01R31/318533
摘要： A test system and method for integrated circuits includes an energy source having an adjustable energy rate, and a feedback device, which measures a physical quantity at a discrete position on an integrated circuit. A control circuit adjusts the power source to externally apply energy to the integrated circuit at the discrete position. A circuit tester applies test programs to the integrated circuit while the discrete position is maintained at a value of the physical quantity in accordance with the control circuit.
摘要翻译：集成电路的测试系统和方法包括具有可调节能量速率的能量源和测量集成电路上的离散位置处的物理量的反馈装置。控制电路调节电源以在离散位置向外部施加能量到集成电路。电路测试仪将测试程序应用于集成电路，而离散位置根据控制电路保持在物理量的值。

3. 发明申请

US20050043908A1 Circuits and methods for characterizing random variations in device characteristics in semiconductor integrated circuits 有权
标题翻译：用于表征半导体集成电路器件特性随机变化的电路和方法
公开(公告)号：US20050043908A1
公开(公告)日：2005-02-24
申请号：US10643193
申请日：2003-08-18
申请人： Azeez Bhavnagarwala , David Frank , Stephen Kosonocky
发明人： Azeez Bhavnagarwala , David Frank , Stephen Kosonocky
IPC分类号： G01R27/28 , G01R31/26 , G01R31/30 , G01R31/317 , G01R31/3173 , G01R31/3193 , G11C29/50
CPC分类号： G11C29/50004 , G01R31/2603 , G01R31/3016 , G01R31/31725 , G01R31/31727 , G01R31/3173 , G01R31/31937 , G11C11/41 , G11C29/50 , G11C2029/5002
摘要： Circuits and methods for measuring and characterizing random variations in device characteristics of semiconductor integrated circuit devices, which enable circuit designers to accurately measure and characterize random variations in device characteristics (such as transistor threshold voltage) between neighboring devices resulting from random sources such as dopant fluctuations and line edge roughness, for purposes of integrated circuit design and analysis. In one aspect, a method for characterizing random variations in device mismatch (e.g., threshold voltage mismatch) between a pair of device (e.g., transistors) is performed by obtaining subthreshold DC voltage characteristic data for the device pair, and then determining a distribution in voltage threshold mismatch for the device pair directly from the corresponding subthreshold DC voltage characteristic data. The voltage threshold mismatch distributions of different device pairs of a given circuit design can then be used to determine voltage threshold variations of the constituent circuit devices. The voltage threshold variation of the devices can be used to characterize the random variations of the given circuit.
摘要翻译：用于测量和表征半导体集成电路器件的器件特性的随机变化的电路和方法，其使电路设计者能够精确地测量和表征由诸如掺杂剂波动的随机源产生的相邻器件之间的器件特性（例如晶体管阈值电压）的随机变化和线边缘粗糙度，用于集成电路设计和分析。在一方面，通过获得器件对的亚阈值DC电压特性数据来执行用于表征一对器件（例如，晶体管）之间的器件失配（例如，阈值电压失配）的随机变化的方法，然后确定器件对中的分布直接从对应的亚阈值直流电压特性数据中的器件对的电压阈值失配。然后可以使用给定电路设计的不同器件对的电压阈值失配分布来确定构成电路器件的电压阈值变化。器件的电压阈值变化可用于表征给定电路的随机变化。

4. 发明申请

US20050018518A1 METHOD AND STRUCTURE FOR REDUCING GATE LEAKAGE AND THRESHOLD VOLTAGE FLUCTUATION IN MEMORY CELLS 失效
标题翻译：用于减少记忆细胞中门的泄漏和阈值电压波动的方法和结构
公开(公告)号：US20050018518A1
公开(公告)日：2005-01-27
申请号：US10625959
申请日：2003-07-24
申请人： Azeez Bhavnagarwala , Stephen Kosonocky
发明人： Azeez Bhavnagarwala , Stephen Kosonocky
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1045 , G11C2207/2227
摘要： A memory device has a memory cell including a plurality of active devices, which can be switched on by an applied threshold voltage. A power line is coupled to at least one storage node by one of the active devices. One other of the active devices couples a virtual ground to the storage node. Potentials of the power line and the virtual ground cause the plurality of active devices to be selectively operated in near subthreshold and/or superthreshold regimes in accordance with a mode of operation.
摘要翻译：存储器件具有包括多个有源器件的存储器单元，其可通过所施加的阈值电压接通。电力线通过一个有源装置耦合到至少一个存储节点。另一个活动设备将虚拟接地耦合到存储节点。根据操作模式，电源线和虚拟接地的电位使多个有源器件选择性地在近临近阈值和/或超阈值状态下操作。

5. 发明申请

US20060064606A1 A METHOD AND APPARATUS FOR CONTROLLING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：一种用于控制集成电路中的功耗的方法和装置
公开(公告)号：US20060064606A1
公开(公告)日：2006-03-23
申请号：US10711485
申请日：2004-09-21
申请人： Suhwan Kim , Stephen Kosonocky , Peter Sandon
发明人： Suhwan Kim , Stephen Kosonocky , Peter Sandon
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3293 , Y02D10/122 , Y02D10/126 , Y02D10/152
摘要： A method and apparatus for controlling power consumption by devices in an integrated circuit. The apparatus includes a complementary device for a corresponding device for which power consumption is desired to be reduced. The complementary device supports all or some of the tasks of the corresponding device. The complementary device receives tasks that can be executed by either itself or the corresponding device and based upon the power management scheme will either execute the task itself or allow the corresponding device.
摘要翻译：一种用于控制集成电路中的器件的功耗的方法和装置。该装置包括用于相应设备的补充设备，期望降低功耗。互补设备支持相应设备的全部或部分任务。互补设备接收可以由其自身或相应设备执行的任务，并且基于功率管理方案将执行任务本身或允许相应的设备。

6. 发明申请

US20050030817A1 Low power circuits with small voltage swing transmission, voltage regeneration, and wide bandwidth architecture 有权
标题翻译：具有小电压摆幅传输，电压再生和宽带宽架构的低功率电路
公开(公告)号：US20050030817A1
公开(公告)日：2005-02-10
申请号：US10635331
申请日：2003-08-06
申请人： Wing Luk , Robert Dennard , Stephen Kosonocky
发明人： Wing Luk , Robert Dennard , Stephen Kosonocky
IPC分类号： G11C5/06 , G11C11/406 , G11C11/4074 , G11C5/00
CPC分类号： G11C5/063 , G11C11/406 , G11C11/4074 , G11C2207/104
摘要： An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.
摘要翻译：诸如存储器宏的集成电路包括支持第一和第二电压差的多个电源轨，第二电压差小于第一电压差。集成电路中的信号线由小的摆动电路产生的小电压摆动驱动。集成电路还包括正在接收小电压摆幅输入并且正在输出第一或全电压摆幅的再生电路。将小电压摆幅应用于信号线节省了集成电路中的功率。宽带宽全字I / O存储器集成电路具有在连接到相同字线和对应的I / O端子的基本上所有存储单元之间的同时可操作的连接路径，并且具有单端数据线结构。

7. 发明申请

US20070247896A1 Static random access memory cell with improved stability 有权
标题翻译：静态随机存取存储单元具有改进的稳定性
公开(公告)号：US20070247896A1
公开(公告)日：2007-10-25
申请号：US11409858
申请日：2006-04-24
申请人： Azeez Bhavnagarwala , Stephen Kosonocky , Sampath Purushothaman , Kenneth Rodbell
发明人： Azeez Bhavnagarwala , Stephen Kosonocky , Sampath Purushothaman , Kenneth Rodbell
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , Y10S257/903
摘要： A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.
摘要翻译：存储单元包括字线，具有第一输入和第一输出的第一数字逆变器以及具有第二输入和第二输出的第二数字反相器。此外，存储单元还包括将第一输出连接到第二输入的第一反馈连接和将第二输出连接到第一输入的第二反馈连接。第一反馈连接包括第一电阻元件，第二反馈连接包括第二电阻元件。更重要的是，每个数字逆变器都有相关的电容。存储单元被配置为使得读取存储器单元包括将读取电压脉冲施加到字线。此外，第一和第二电阻元件被配置为使得第一和第二反馈连接具有比施加的读取电压脉冲更长的电阻 - 电容感应延迟。

8. 发明申请

US20050285628A1 Charge recycling power gate 失效
标题翻译：充电回收电源门
公开(公告)号：US20050285628A1
公开(公告)日：2005-12-29
申请号：US10880111
申请日：2004-06-29
申请人： Suhwan Kim , Daniel Knebel , Stephen Kosonocky
发明人： Suhwan Kim , Daniel Knebel , Stephen Kosonocky
IPC分类号： H03K19/00 , H03K19/094
CPC分类号： H03K19/0019
摘要： A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.
摘要翻译：提供电荷回收功率门和相应的方法，用于使用功能单元的电容性负载与电荷回收装置的寄生电容之间的电荷共享效应，以接通虚拟地面和地面之间的开关装置，电荷回收功率门，包括第一晶体管，与第一晶体管的第一端子进行信号通信的虚拟地，与第一晶体管的第二端子进行信号通信的地，电容器，具有与第三晶体管的第三端子信号通信的第一端子第一晶体管和与地面信号通信的第二端子，以及第二晶体管，其具有与虚拟接地信号通信的第一端子和与第一晶体管的第三端子信号通信的第二端子。

9. 发明申请

US20050047196A1 Loadless NMOS four transistor dynamic dual Vt SRAM cell 有权
标题翻译：无负载NMOS四晶体管动态双Vt SRAM单元
公开(公告)号：US20050047196A1
公开(公告)日：2005-03-03
申请号：US10649200
申请日：2003-08-27
申请人： Azeez Bhavnagarwala , Rajiv Joshi , Stephen Kosonocky
发明人： Azeez Bhavnagarwala , Rajiv Joshi , Stephen Kosonocky
IPC分类号： G11C11/418 , G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： G11C11/412
摘要： Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T SRAM cell comprises a pair of access transistors and a pair of pull-down transistors, all of which are implemented as N-channel transistors (NFETs or NMOSFETS). The access transistors have lower threshold voltages than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “1” potential during standby. The pull-down transistors have larger channel widths as compared to the access transistors, which enables the SRAM cell to effectively maintain a logic “0” potential at a given storage node during a read operation. A method is implemented for dynamically adjusting the threshold voltages of the transistors of activated memory cells during an access operation to thereby increase the read current or performance of the accessed memory cells.
摘要翻译：无负载4T SRAM单元以及用于操作这样的SRAM单元的方法，其可以提供高度集成的半导体存储器件，同时在数据访问操作方面提供相对于数据稳定性和增加的I / O速度的增加的性能。无负载的4T SRAM单元包括一对存取晶体管和一对下拉晶体管，所有这些都被实现为N沟道晶体管（NFET或NMOSFETS）。存取晶体管具有比下拉晶体管低的阈值电压，这使得SRAM单元能够在待机期间有效地保持逻辑“1”电位。与存取晶体管相比，下拉晶体管具有较大的沟道宽度，这使得SRAM单元能够在读取操作期间在给定存储节点处有效地保持逻辑“0”电位。实现了一种用于在访问操作期间动态地调整激活的存储器单元的晶体管的阈值电压从而增加所访问的存储器单元的读取电流或性能的方法。

10. 发明申请

US20050024113A1 METHODS AND APPARATUS FOR EMPLOYING FEEDBACK BODY CONTROL IN CROSS-COUPLED INVERTERS 失效
标题翻译：在交叉耦合逆变器中采用反馈体控制的方法和装置
公开(公告)号：US20050024113A1
公开(公告)日：2005-02-03
申请号：US10604554
申请日：2003-07-30
申请人： Paul Kartschoke , Stephen Kosonocky , Randy Mann , Norman Rohrer
发明人： Paul Kartschoke , Stephen Kosonocky , Randy Mann , Norman Rohrer
IPC分类号： H03K3/037 , H03K3/356
CPC分类号： H03K3/356104 , H03K3/0375
摘要： In a first aspect, a cross-coupled inverter is provided that includes a first inverter circuit having a first NFET coupled to a first PFET and a second inverter circuit having a second NFET coupled to a second PFET. The second inverter circuit is cross-coupled with the first inverter circuit at a plurality of nodes. The body of at least one of the first NFET, the second NFET, the first PFET and the second PFET is coupled so as to form a feedback path that reduces discharging at one or more of the plurality of nodes in response to a soft error event at the cross-coupled inverter.
摘要翻译：在第一方面，提供一种交叉耦合的反相器，其包括具有耦合到第一PFET的第一NFET的第一反相器电路和具有耦合到第二PFET的第二NFET的第二反相器电路。第二逆变器电路在多个节点处与第一反相器电路交叉耦合。第一NFET，第二NFET，第一PFET和第二PFET中的至少一个的主体被耦合以形成反馈路径，其减少响应于软错误事件的多个节点中的一个或多个的放电在交叉耦合的逆变器。

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