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1. 发明授权

US06529402B1 Low power static memory 有权
标题翻译：低功耗静态存储器
公开(公告)号：US06529402B1
公开(公告)日：2003-03-04
申请号：US10094533
申请日：2002-03-08
申请人： John E. Andersen , Louis Lu-Chen Hsu , Li-Kong Wang
发明人： John E. Andersen , Louis Lu-Chen Hsu , Li-Kong Wang
IPC分类号： G11C1100
CPC分类号： G11C11/417 , G11C5/025 , G11C8/08
摘要： A stacked block array architecture.for a SRAM memory for low power applications. The architecture turns on only the required data cells and sensing circuitry to access a particular set of data cells of interest. The wordline delay is reduced by using a shorter and wider wordline wire size. Although less power is consumed, the performance is improved by the reduction in loading of wordlines and bitlines.
摘要翻译：堆叠块阵列架构，用于低功耗应用的SRAM存储器。该架构仅打开所需的数据单元和感测电路以访问感兴趣的特定数据单元组。通过使用更短和更宽的字线大小减小字线延迟。虽然功耗较低，但通过减少字线和位线的负载来提高性能。

2. 发明授权

US06656751B2 Self test method and device for dynamic voltage screen functionality improvement 失效
标题翻译：用于动态电压屏幕功能改进的自检方法和装置
公开(公告)号：US06656751B2
公开(公告)日：2003-12-02
申请号：US09683050
申请日：2001-11-13
申请人： John E. Andersen , Bruce M. Cowan , Pamela S. Gillis , Steven F. Oakland , Michael R. Ouellette
发明人： John E. Andersen , Bruce M. Cowan , Pamela S. Gillis , Steven F. Oakland , Michael R. Ouellette
IPC分类号： H01L2100
CPC分类号： G11C29/12015 , G01R31/31724 , G01R31/3187 , G11C29/14 , H03K5/135
摘要： Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.
摘要翻译：公开了一种包括内置自检控制器的装置，其具有用于提供指示是否正在执行动态电压屏幕（DVS）测试的接口信号的机制。自检控制器与包括具有时钟速度的时钟的存储器阵列相关联。存储器阵列还包括时钟调节器，当接口信号指示正在执行DVS测试时，时钟调节器接收接口信号并降低时钟速度。

3. 发明授权

US5040145A Memory cell with active write load 失效
标题翻译：具有活动写入负载的存储单元
公开(公告)号：US5040145A
公开(公告)日：1991-08-13
申请号：US505952
申请日：1990-04-06
申请人： John E. Andersen , Robert L. Barry , James N. Bisnett , Eric G. Fung
发明人： John E. Andersen , Robert L. Barry , James N. Bisnett , Eric G. Fung
IPC分类号： G11C11/411 , G11C11/416
CPC分类号： G11C11/416 , G11C11/4113
摘要： A memory cell responsive to a write enable signal for storing write signals present on a pair of write bit lines and responsive to a read enable signal for presenting stored data on a pair of read sense lines further includes a timed, active write load. The memory cell includes first and second NPN bipolar transistors having commonly connected emitters, and cross-coupled bases and collectors; and first and second PNP bipolar transistors configured as loads for the pair of NPN bipolar transistors. Write transistors are provided responsive to the write enable signal for draining current from a selected one of the first or second nodes. Transistors connected as diodes between the PNP bases and each of the cross-coupled NPN nodes are responsive to the current draining effected by the write transistors for biasing both of the first and second PNP transistors into an active mode of operation.
摘要翻译：响应于写入使能信号的存储单元，用于存储存在于一对写入位线上的写入信号，并且响应用于在一对读取检测线上呈现存储的数据的读取使能信号进一步包括定时的有效写入负载。存储单元包括具有共同连接的发射极的第一和第二NPN双极晶体管，以及交叉耦合的基极和集电极; 以及配置为一对NPN双极晶体管的负载的第一和第二PNP双极晶体管。响应于写使能信号提供写晶体管，用于从第一或第二节点中选定的一个节点排出电流。在PNP基极和每个交叉耦合的NPN节点之间以二极管连接的晶体管响应于由写入晶体管实现的电流引流，用于将第一和第二PNP晶体管的两者均匀化成主动操作模式。

4. 发明授权

US4616341A Directory memory system having simultaneous write and comparison data bypass capabilities 失效
标题翻译：具有同时写入和比较数据旁路能力的目录存储器系统
公开(公告)号：US4616341A
公开(公告)日：1986-10-07
申请号：US509674
申请日：1983-06-30
申请人： John E. Andersen , Joseph A. Petrosky , Benedicto U. Messina , William D. Silkman
发明人： John E. Andersen , Joseph A. Petrosky , Benedicto U. Messina , William D. Silkman
IPC分类号： G06F12/00 , G06F7/02 , G06F12/02 , G06F12/08 , G06F17/30 , G11C7/00
CPC分类号： G06F17/30952 , G06F12/0888 , G06F7/02
摘要： A directory memory system having simultaneous writing and bypass capabilities. A data output bit from a respective memory cell of a memory array is applied to a control input of a first differential amplifier, while comparison input data is applied to inputs of a second differential amplifier. The outputs of corresponding transistors of the two differential amplifiers are connected together. Current switch transistors, operated in response to a bypass select signal, supply current only to one or the other of the two differential amplifiers. The differential output signal produced across the commonly connected outputs of the two differential amplifier circuits is buffered and amplified with a push-pull output circuit.
摘要翻译：具有同时写入和旁路能力的目录存储器系统。来自存储器阵列的相应存储单元的数据输出位被施加到第一差分放大器的控制输入，而比较输入数据被施加到第二差分放大器的输入。两个差分放大器的相应晶体管的输出端连接在一起。电流开关晶体管响应于旁路选择信号而工作，仅向两个差分放大器中的一个或另一个供电。在两个差分放大器电路的共同连接的输出端产生的差分输出信号被缓冲并用推挽输出电路放大。

5. 发明授权

US06434076B1 Refresh control circuit for low-power SRAM applications 有权
标题翻译：刷新控制电路，用于低功耗SRAM应用
公开(公告)号：US06434076B1
公开(公告)日：2002-08-13
申请号：US09766799
申请日：2001-01-22
申请人： John E. Andersen , Louis L. Hsu , Stephen Kosonocky , Li-Kong Wang
发明人： John E. Andersen , Louis L. Hsu , Stephen Kosonocky , Li-Kong Wang
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C11/406
摘要： A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to local supplies during an active mode of operation. The power management circuit comprises: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory array refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode. During the low power mode, the refresh circuit intentionally enables the local power supply to float and allow it to drift to a lower predetermined voltage level prior to the memory array refresh operation.
摘要翻译：一种用于SRAM系统的电源管理电路，包括一个或多个隔离存储器阵列，并且在主动操作模式期间实现包括与每个存储器阵列相关联的本地电源的电源和连接到本地电源的外部电源。电源管理电路包括：开关机构，用于在低功率操作模式期间断开外部电源到每个本地电源; 以及通过在低功率模式期间选择性地将外部电源连接到各个本地电源来实现存储器阵列刷新操作的刷新定时电路。在低功率模式期间，刷新电路有意地使本地电源浮动并允许其在存储器阵列刷新操作之前漂移到较低的预定电压电平。

6. 发明授权

US06363023B1 Bi-directional differential low power sense amp and memory system 有权
公开(公告)号：US06363023B1
公开(公告)日：2002-03-26
申请号：US09792959
申请日：2001-02-26
申请人： John E. Andersen , Michael R. Ouellette
发明人： John E. Andersen , Michael R. Ouellette
IPC分类号： G11C702
摘要： A device and method is provided for reducing power consumption in memory devices. The preferred embodiment reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.

7. 发明授权

US4663742A Directory memory system having simultaneous write, compare and bypass capabilites 失效
标题翻译：具有同时写入，比较和旁路能力的目录存储器系统
公开(公告)号：US4663742A
公开(公告)日：1987-05-05
申请号：US666580
申请日：1984-10-30
申请人： John E. Andersen , Robert L. Barry , Kenneth H. Christie , Dennis J. Shea
发明人： John E. Andersen , Robert L. Barry , Kenneth H. Christie , Dennis J. Shea
IPC分类号： G06F12/08 , G06F17/30 , G11C7/00
CPC分类号： G06F17/30982
摘要： A directory memory system including a plurality of reconfigurable subarrays of memory cells and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays. Output data from the subarrays is connected to compare data logic for comparing the subarray data to one or more bytes of compare input data, and to bit select logic for selectively placing the subarray data onto an output bus. Bypass select logic causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays, and one byte of compare input data can be bypassed to the data output port during the compare operation. Additionally, data may be written into the subarrays while simultaneously performing the compare or the compare/bypass operation.
摘要翻译：包括存储器单元的多个可重构子阵列并且具有同时执行写/比，读/比，比较/旁路，写/旁路或写/比/旁路操作的能力的目录存储器系统。本系统可以制造在单个集成电路芯片上，并且包括用于将数据选择性地写入子阵列的电路。连接来自子阵列的输出数据以比较用于将子阵列数据与比较输入数据的一个或多个字节进行比较的数据逻辑，以及用于选择性地将子阵列数据放置到输出总线上的比特选择逻辑。旁路选择逻辑会导致从存储器系统数据输出端口输出子阵列数据或比较数据的一个字节。在一个实施例中，两个字节的比较输入数据可以与来自每个子阵列的所选数据字节同时进行比较，并且比较输入数据的一个字节可以在比较操作期间被旁路到数据输出端口。此外，数据可以写入子阵列，同时执行比较或比较/旁路操作。

8. 发明授权

US06307805B1 High performance semiconductor memory device with low power consumption 有权
标题翻译：高性能半导体存储器件，功耗低
公开(公告)号：US06307805B1
公开(公告)日：2001-10-23
申请号：US09745227
申请日：2000-12-21
申请人： John E. Andersen , Terence B. Hook , Louis L. Hsu , Wei Hwang , Stephen V. Kosonocky , Li-Kong Wang
发明人： John E. Andersen , Terence B. Hook , Louis L. Hsu , Wei Hwang , Stephen V. Kosonocky , Li-Kong Wang
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C11/418 , H01L27/11
摘要： A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.
摘要翻译：用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。

9. 发明授权

US06249470B1 Bi-directional differential low power sense amp and memory system 有权
标题翻译：双向差分低功率检测放大器和存储器系统
公开(公告)号：US06249470B1
公开(公告)日：2001-06-19
申请号：US09454265
申请日：1999-12-03
申请人： John E. Andersen , Michael R. Ouellette
发明人： John E. Andersen , Michael R. Ouellette
IPC分类号： G11C702
CPC分类号： G11C11/419 , G11C7/065
摘要： According to the preferred embodiment, a device and method is provided for reducing power consumption in memory devices. The preferred embodiment reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment, the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.
摘要翻译：根据优选实施例，提供了一种用于降低存储器件中的功耗的装置和方法。优选实施例通过提供在提供高性能的同时降低功耗的读出放大器来降低功耗。在优选实施例中，读出放大器包括可配置用于低功率静态随机存取存储器（SRAM）器件的双向读出放大器。双向读出放大器允许将相同的感测放大器用于存储器单元上的读取和写入操作。优选实施例的感测放大器有助于使用差分数据总线，进一步降低功耗，同时提供高性能。因此，优选实施例的双向差分检测放大器降低了器件尺寸和复杂性，降低了功耗，同时提供了高性能的存储器访问。

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