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1. 发明授权

US06373771B1 Integrated fuse latch and shift register for efficient programming and fuse readout 有权
标题翻译：集成保险丝锁存器和移位寄存器，用于高效编程和保险丝读出
公开(公告)号：US06373771B1
公开(公告)日：2002-04-16
申请号：US09765035
申请日：2001-01-17
申请人： John A. Fifield , Wayne F. Ellis , Nicholas M. van Heel
发明人： John A. Fifield , Wayne F. Ellis , Nicholas M. van Heel
IPC分类号： G11C700
CPC分类号： G11C29/52 , G11C17/16 , G11C17/18 , G11C19/00 , G11C29/006 , G11C29/50
摘要： An integrated circuit device that obviates laser programming of a two-state element (e.g., a wire fuse or antifuse) by programming (i.e., changing) the conductive state of the two-state element according to a binary bit of programing data serially scanned in. Thereafter, the device can verify the actual programming of the two-state element by sensing the conducting condition and then serially scanning out the conductive state value of the two-sate element as a binary logic bit). The device provides the functionality of being able to test any on-chip non-memory circuitry that depends on a memory circuit being fully functional and operational while still at the wafer tester and before having to “blow” (i.e., program) any fuses.
摘要翻译：一种集成电路器件，其通过根据串行扫描的编程数据的二进制位编程（即，改变）两状态元件的导通状态来消除双状态元件（例如，线熔丝或反熔丝）的激光编程此后，器件可以通过感测导通条件来验证双态元件的实际编程，然后串行扫描两元件的导通状态值作为二进制逻辑位）。该器件提供了能够测试任何片上非存储器电路的功能，该片上非存储器电路取决于完全功能和可操作的存储器电路，同时仍然在晶片测试器处，并且在必须“吹”（即编程）任何保险丝之前。

2. 发明授权

US06420925B1 Programmable latch device with integrated programmable element 有权
标题翻译：具有集成可编程元件的可编程锁存器件
公开(公告)号：US06420925B1
公开(公告)日：2002-07-16
申请号：US09757267
申请日：2001-01-09
申请人： John A. Fifield , Erik L. Hedberg , Claude L. Bertin , Nicholas M. van Heel
发明人： John A. Fifield , Erik L. Hedberg , Claude L. Bertin , Nicholas M. van Heel
IPC分类号： H01H3776
CPC分类号： H03K3/356008 , G11C17/18
摘要： According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.
摘要翻译：根据本发明，提供了用于个性化半导体器件的可编程锁存器件，其克服了现有技术的限制。优选实施例可编程锁存器件可以使用熔丝和反熔丝作为可编程元件。可编程锁存器件提供指示可编程器件状态的实心数字输出，并且可被可靠地读取以提供相关半导体器件的定制和个性化。优选实施例可编程锁存装置包括作为锁存装置中的可编程元件的集成熔丝或反熔丝。通过将可编程元件集成到锁存器中，器件尺寸和复杂度最小化。特别地，与现有技术方法相比，所需的晶体管的数量显着下降。

3. 发明授权

US06400202B1 Programmable delay element and synchronous DRAM using the same 失效
标题翻译：可编程延迟元件和同步DRAM
公开(公告)号：US06400202B1
公开(公告)日：2002-06-04
申请号：US09988846
申请日：2001-11-19
申请人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
发明人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
IPC分类号： G06F104
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译：可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。电流源FET栅极可编程，预定量的电流。耦合到电流源PET的开关装置接收具有第一和第二电压电平的输入信号。当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。

4. 发明授权

US06346846B1 Methods and apparatus for blowing and sensing antifuses 失效
标题翻译：用于吹制和检测反熔丝的方法和装置
公开(公告)号：US06346846B1
公开(公告)日：2002-02-12
申请号：US09466479
申请日：1999-12-17
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
IPC分类号： H01H3776
CPC分类号： G11C5/145 , G11C17/18
摘要： Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.
摘要翻译：提供了用于吹制和检测反熔丝的方法和装置。具体地，在第一方面中，提供一种通过选择一组反熔丝中的一个并且施加高电压来改变所选择的反熔丝的状态来改变多个反熔丝之一的状态的方法。在第二和第三方面中，提供了用于执行第一方面的方法的装置。在第四方面，提供了一种用于升压电压的方法，包括以下步骤：在第一级升压电路的第一级存储机构内产生第一电压，产生等于第一级升压电路中第一电压的大约两倍的第二电压，第二级升压电路的第二级第二级存储机构，并且基于第二级升压电路的第二电压产生约三倍的第一电压。在第五方面中，提供了用于执行第四方面的方法的装置。

5. 发明授权

US06452439B1 Inductive voltage spike generator with diode shunt 失效
标题翻译：具有二极管分流的感应电压尖峰发生器
公开(公告)号：US06452439B1
公开(公告)日：2002-09-17
申请号：US09850353
申请日：2001-05-07
申请人： John A. Fifield , Nicholas M. Van heel
发明人： John A. Fifield , Nicholas M. Van heel
IPC分类号： G05F110
CPC分类号： H01L23/62 , H01L23/5256 , H01L23/58 , H01L2224/48091 , H01L2224/49171 , H01L2924/30107 , H02M3/155 , H01L2924/00014 , H01L2924/00
摘要： A voltage generator for an integrated circuit chip comprises an integrated circuit chip with a power supply having a voltage available to the chip; an inductor on or in contact with the integrated circuit chip electrically connected to the power supply through which current is driven; and a clock adapted to interrupting current flowing from the power supply through the inductor at desired time intervals to create voltage spikes above the power supply voltage. The inductor may comprise a portion of the lead frame connecting the integrated circuit chip to an integrated chip package. The voltage spikes generate a voltage about two or more times the voltage of the power supply available to the chip. Where the integrated circuit chip includes an electrical fuse and/or a battery, the fuse on the chip may be adapted to be programmed or the battery charged by the voltage spikes.
摘要翻译：一种用于集成电路芯片的电压发生器包括具有电源可用于芯片的电源的集成电路芯片; 与集成电路芯片接触或接触的电感器，其电连接到通过其驱动电流的电源; 以及适于以期望的时间间隔中断从电源流过电感器的电流以在电源电压之上产生电压尖峰的时钟。电感器可以包括将集成电路芯片连接到集成芯片封装的引线框架的一部分。电压尖峰产生大约是芯片可用电源电压的两倍或更多倍的电压。在集成电路芯片包括电熔丝和/或电池的情况下，芯片上的保险丝可能被编程或由电压尖峰充电的电池。

6. 发明授权

US06384666B1 Antifuse latch device with controlled current programming and variable trip point 有权
标题翻译：具有受控电流编程和可变跳变点的防漏锁存器件
公开(公告)号：US06384666B1
公开(公告)日：2002-05-07
申请号：US09816030
申请日：2001-03-23
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Nicholas M. van Heel
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Nicholas M. van Heel
IPC分类号： H01H3776
CPC分类号： G11C17/18
摘要： A latch device is provided having a variable resistive trip point and controlled current programming. The latch device has a trip point current control element that controls an amount of current passing from a voltage source into the latch circuit, thereby varying the resistive trip point of the latch device. The latch device also has a programming current control element that controls an amount of programming current passing through the fuse element during programming. The trip point current reference and a programming current reference are provided by reference circuits having a plurality of selectable inputs that operate to change the current references binarily. An integrated circuit is also provided in which a plurality of the fuse latch devices are connected together in parallel such that the same trip point current reference and programming current reference are supplied to each latch device.
摘要翻译：提供具有可变电阻跳变点和受控电流编程的锁存器件。闩锁装置具有跳闸电流控制元件，其控制从电压源流入锁存电路的电流量，从而改变闩锁装置的电阻性跳变点。闩锁装置还具有编程电流控制元件，其控制在编程期间通过熔丝元件的编程电流量。跳变点电流基准和编程电流基准由具有多个可选择输入的参考电路提供，所述多个可选输入用于二次改变当前基准。还提供一种集成电路，其中多个熔丝锁存器件并联连接在一起，使得相同的跳变点电流参考和编程电流基准被提供给每个锁存器件。

7. 发明授权

US06348827B1 Programmable delay element and synchronous DRAM using the same 失效
标题翻译：可编程延迟元件和同步DRAM
公开(公告)号：US06348827B1
公开(公告)日：2002-02-19
申请号：US09501216
申请日：2000-02-10
申请人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
发明人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
IPC分类号： H03H1126
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译：可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。电流源FET栅极可编程，预定量的电流。耦合到电流源FET的开关器件接收具有第一和第二电压电平的输入信号。当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。

8. 发明授权

US07305515B2 Performance optimizing compiler for building a compiled DRAM 失效
标题翻译：用于构建编译的DRAM的性能优化编译器
公开(公告)号：US07305515B2
公开(公告)日：2007-12-04
申请号：US09793037
申请日：2001-02-26
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F17/5045
摘要： A compiler is provided for compiling at least one array or bank unit of a DRAM macro such that electrical performance, including cycle time, access time, setup time, among other properties, is optimized. The compiler compiles the DRAM macro according to inputted information. The compiler receives an input capacity and configuration for the DRAM macro. A compiler algorithm determines a number of wordlines and bitlines required to create the DRAM macro of the input capacity. The compiler algorithm optimizes the cycle time and access time of the DRAM macro by properly configuring a support unit of the DRAM macro based upon the number of wordlines and bitlines.
摘要翻译：提供了一种用于编译DRAM宏的至少一个阵列或存储体单元的编译器，使得包括循环时间，访问时间，建立时间在内的电性能以及其他特性被优化。编译器根据输入的信息编译DRAM宏。编译器接收DRAM宏的输入容量和配置。编译器算法确定创建输入容量的DRAM宏所需的字数和位线数。编译器算法通过根据字线和位线的数量正确配置DRAM宏的支持单元来优化DRAM宏的周期时间和访问时间。

9. 发明授权

US07085971B2 ECC based system and method for repairing failed memory elements 失效
标题翻译：基于ECC的系统和修复失败的内存元素的方法
公开(公告)号：US07085971B2
公开(公告)日：2006-08-01
申请号：US10035474
申请日：2001-10-25
申请人： John E. Barth, Jr. , Wayne F. Ellis , John A. Fifield
发明人： John E. Barth, Jr. , Wayne F. Ellis , John A. Fifield
IPC分类号： G11C29/00
CPC分类号： G11C29/72 , G11C29/42 , G11C29/789 , G11C2029/4402
摘要： An ECC based system and method within an integrated circuit memory for self-repair of a failed memory element is disclosed. The method includes processing, within the integrated circuit, data and check bits retrieved from addressed memory locations therein. The locations of memory failures are automatically recorded within the integrated circuit. Logic circuits within the integrated circuit automatically identify failure patterns based on the locations. Based on the identified failure patterns, logic circuits within the integrated circuit then permanently replace a failed memory element with an appropriate redundancy element, using devices such as electronic fuse or antifuse. In this manner, the integrated circuit automatically identifies and effects self repair of a failed memory element therein.
摘要翻译：公开了一种用于故障存储器元件的自修复的集成电路存储器内的基于ECC的系统和方法。该方法包括在集成电路内处理从其中的寻址的存储器位置检索的数据和校验位的处理。内存故障的位置会自动记录在集成电路中。集成电路内的逻辑电路根据位置自动识别故障模式。基于所识别的故障模式，集成电路内的逻辑电路然后使用诸如电子熔断器或反熔丝的装置用适当的冗余元件永久地替换故障存储器元件。以这种方式，集成电路自动识别并实现其中的故障存储元件的自身修复。

10. 发明授权

US06538932B2 Timing circuit and method for a compilable DRAM 有权
标题翻译：可编程DRAM的定时电路和方法
公开(公告)号：US06538932B2
公开(公告)日：2003-03-25
申请号：US09880598
申请日：2001-06-13
申请人： Wayne F. Ellis , John A. Fifield , Louis L. Hsu
发明人： Wayne F. Ellis , John A. Fifield , Louis L. Hsu
IPC分类号： G11C700
CPC分类号： G11C11/4096 , G11C7/1051 , G11C7/22 , G11C11/4076 , G11C2207/2281
摘要： A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.
摘要翻译：公开了一种半导体存储器，所述存储器包括：适于存储位的存储器单元; 耦合到存储器单元的字线和位线; 当所述字线有效时，耦合到所述位线的初级读出放大器接收表示存储位的信号; 耦合以激活字线的字线驱动器; 以及适于产生从可选延迟的范围中选择的第一延迟的主延迟装置，所述主延迟装置适于补偿沿着字线的信号传播延迟。

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