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1. 发明授权

US06658604B1 Method for testing and guaranteeing that skew between two signals meets predetermined criteria 失效
标题翻译：用于测试和保证两个信号之间的偏差达到预定标准的方法
公开(公告)号：US06658604B1
公开(公告)日：2003-12-02
申请号：US09685939
申请日：2000-10-10
申请人： William R. Corbin , David P. Monty , Erik A. Nelson , Alan D. Norris , Steven W. Tomashot , David E. Chapman , Timothy E. Fiscus
发明人： William R. Corbin , David P. Monty , Erik A. Nelson , Alan D. Norris , Steven W. Tomashot , David E. Chapman , Timothy E. Fiscus
IPC分类号： G11B2020
CPC分类号： G11C29/028 , G01R31/3016 , G01R31/31937 , G11C11/401 , G11C29/50 , G11C29/50012 , H04L25/14
摘要： To overcome these problems, the present invention generates two window strobes and uses the two window strobes to determine if skew between two signals meets predetermined criteria. One of the window strobes is used to test one of the signals, and the other window strobe is generated relative to the first window strobe. The second window strobe tests the other signal (or signals, if they are data signals). From the tests of the two window strobes, it can be determined if the skew between the first and second signals meets predetermined criteria. In particular, the two window strobes are placed relative to each other and to the signals being tested in such a way that when both window strobes indicate passing conditions, skew between the two signals is guaranteed.
摘要翻译：为了克服这些问题，本发明产生两个窗口选通信号并使用两个窗口选通来确定两个信号之间的偏斜是否满足预定标准。窗口选通中的一个用于测试信号之一，并且相对于第一窗口选通产生另一个窗口选通。第二个窗口频闪测试其他信号（或信号，如果它们是数据信号）。从两个窗口选通的测试中，可以确定第一和第二信号之间的偏差是否满足预定标准。特别地，两个窗口闪光灯相对于彼此放置并且被测试的信号以这样的方式放置，即当两个窗口闪光灯指示通过条件时，两个信号之间的偏移被保证。

2. 发明授权

US06400202B1 Programmable delay element and synchronous DRAM using the same 失效
标题翻译：可编程延迟元件和同步DRAM
公开(公告)号：US06400202B1
公开(公告)日：2002-06-04
申请号：US09988846
申请日：2001-11-19
申请人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
发明人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
IPC分类号： G06F104
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译：可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。电流源FET栅极可编程，预定量的电流。耦合到电流源PET的开关装置接收具有第一和第二电压电平的输入信号。当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。

3. 发明授权

US06618314B1 Method and architecture for reducing the power consumption for memory devices in refresh operations 有权
标题翻译：用于降低刷新操作中存储器件功耗的方法和架构
公开(公告)号：US06618314B1
公开(公告)日：2003-09-09
申请号：US10090850
申请日：2002-03-04
申请人： Timothy E. Fiscus , David E. Chapman , Richard M. Parent
发明人： Timothy E. Fiscus , David E. Chapman , Richard M. Parent
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) enabling the background operations in one or more sections of the memory array when one or more control signals are in a first state and disabling the background operations in one or more sections of the memory array when the one or more control signals are in a second state and (ii) generating the one or more control signals in response to an address signal.
摘要翻译：一种用于在具有多个部分的存储器阵列中的后台操作期间降低功耗的方法，包括以下步骤：（i）当一个或多个控制信号处于第一状态时，使得能够在所述存储器阵列的一个或多个部分中进行背景操作;以及当所述一个或多个控制信号处于第二状态时，禁用所述存储器阵列的一个或多个部分中的后台操作，以及（ii）响应于地址信号产生所述一个或多个控制信号。

4. 发明授权

US06708298B2 Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devices 有权
标题翻译：用于保证DDR存储器件的最小数据选通有效窗口和最小数据有效窗口的方法
公开(公告)号：US06708298B2
公开(公告)日：2004-03-16
申请号：US09768122
申请日：2001-01-23
申请人： William E. Corbin, Jr. , David P. Monty , Erik A. Nelson , Alan D. Norris , Steven W. Tomashot , David E. Chapman , Timothy E. Fiscus
发明人： William E. Corbin, Jr. , David P. Monty , Erik A. Nelson , Alan D. Norris , Steven W. Tomashot , David E. Chapman , Timothy E. Fiscus
IPC分类号： G11C2900
CPC分类号： G11C29/50012 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C29/50
摘要： A method for testing the data strobe window (DQS) and data valid window (tDV) of a memory device (e.g., a DDR-type memory device) using the window strobe of a testing system.
摘要翻译：一种使用测试系统的窗口选通来测试存储器件（例如，DDR型存储器件）的数据选通窗口（DQS）和数据有效窗口（tDV）的方法。

5. 发明授权

US07064596B1 Reducing crowbar current in a latch hysteresis receiver 有权
标题翻译：减少锁存滞后接收器中的撬棒电流
公开(公告)号：US07064596B1
公开(公告)日：2006-06-20
申请号：US10327571
申请日：2002-12-20
申请人： Christopher L. Smith , David E. Chapman
发明人： Christopher L. Smith , David E. Chapman
IPC分类号： H09K3/12
CPC分类号： H03K3/012 , H03K3/356165 , H03K3/3565
摘要： One embodiment of the present invention provides a latch hysteresis receiver circuit having reduced crowbar current. Within the present embodiment, the latch hysteresis receiver circuit comprises an input stage and a latch hysteresis switching element coupled to the input stage. Additionally, the latch hysteresis receiver circuit comprises a pass gate coupled to the latch hysteresis switching element and to an output of the latch hysteresis receiver circuit. It is noted that the pass gate may be for restricting current that flows through the latch hysteresis switching element.
摘要翻译：本发明的一个实施例提供了具有减小的撬棒电流的锁存滞后接收器电路。在本实施例中，锁存滞后接收器电路包括耦合到输入级的输入级和锁存滞后开关元件。此外，锁存滞后接收器电路包括耦合到锁存滞后开关元件的通过栅极和锁存滞后接收器电路的输出。注意，通路可以用于限制流过锁存滞后开关元件的电流。

6. 发明授权

US07057960B1 Method and architecture for reducing the power consumption for memory devices in refresh operations 有权
标题翻译：用于降低刷新操作中存储器件功耗的方法和架构
公开(公告)号：US07057960B1
公开(公告)日：2006-06-06
申请号：US10629667
申请日：2003-07-29
申请人： Timothy E. Fiscus , David E. Chapman , Richard M. Parent
发明人： Timothy E. Fiscus , David E. Chapman , Richard M. Parent
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) controlling the background operations in one or more sections of the memory array in response to one or more control signals and (ii) presenting the one or more control signals and one or more decoded address signals to one or more periphery array circuits of the one or more sections.
摘要翻译：一种用于在具有多个部分的存储器阵列中的背景操作期间降低功耗的方法，包括以下步骤：（i）响应于一个或多个控制信号控制所述存储器阵列的一个或多个部分中的后台操作，以及（ii）将一个或多个控制信号和一个或多个解码的地址信号呈现给所述一个或多个部分的一个或多个外围阵列电路。

7. 发明授权

US06348827B1 Programmable delay element and synchronous DRAM using the same 失效
标题翻译：可编程延迟元件和同步DRAM
公开(公告)号：US06348827B1
公开(公告)日：2002-02-19
申请号：US09501216
申请日：2000-02-10
申请人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
发明人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
IPC分类号： H03H1126
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译：可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。电流源FET栅极可编程，预定量的电流。耦合到电流源FET的开关器件接收具有第一和第二电压电平的输入信号。当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。

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