专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06420925B1 Programmable latch device with integrated programmable element 有权
标题翻译：具有集成可编程元件的可编程锁存器件
公开(公告)号：US06420925B1
公开(公告)日：2002-07-16
申请号：US09757267
申请日：2001-01-09
申请人： John A. Fifield , Erik L. Hedberg , Claude L. Bertin , Nicholas M. van Heel
发明人： John A. Fifield , Erik L. Hedberg , Claude L. Bertin , Nicholas M. van Heel
IPC分类号： H01H3776
CPC分类号： H03K3/356008 , G11C17/18
摘要： According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.
摘要翻译：根据本发明，提供了用于个性化半导体器件的可编程锁存器件，其克服了现有技术的限制。优选实施例可编程锁存器件可以使用熔丝和反熔丝作为可编程元件。可编程锁存器件提供指示可编程器件状态的实心数字输出，并且可被可靠地读取以提供相关半导体器件的定制和个性化。优选实施例可编程锁存装置包括作为锁存装置中的可编程元件的集成熔丝或反熔丝。通过将可编程元件集成到锁存器中，器件尺寸和复杂度最小化。特别地，与现有技术方法相比，所需的晶体管的数量显着下降。

2. 发明授权

US06400202B1 Programmable delay element and synchronous DRAM using the same 失效
标题翻译：可编程延迟元件和同步DRAM
公开(公告)号：US06400202B1
公开(公告)日：2002-06-04
申请号：US09988846
申请日：2001-11-19
申请人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
发明人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
IPC分类号： G06F104
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译：可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。电流源FET栅极可编程，预定量的电流。耦合到电流源PET的开关装置接收具有第一和第二电压电平的输入信号。当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。

3. 发明授权

US06373771B1 Integrated fuse latch and shift register for efficient programming and fuse readout 有权
标题翻译：集成保险丝锁存器和移位寄存器，用于高效编程和保险丝读出
公开(公告)号：US06373771B1
公开(公告)日：2002-04-16
申请号：US09765035
申请日：2001-01-17
申请人： John A. Fifield , Wayne F. Ellis , Nicholas M. van Heel
发明人： John A. Fifield , Wayne F. Ellis , Nicholas M. van Heel
IPC分类号： G11C700
CPC分类号： G11C29/52 , G11C17/16 , G11C17/18 , G11C19/00 , G11C29/006 , G11C29/50
摘要： An integrated circuit device that obviates laser programming of a two-state element (e.g., a wire fuse or antifuse) by programming (i.e., changing) the conductive state of the two-state element according to a binary bit of programing data serially scanned in. Thereafter, the device can verify the actual programming of the two-state element by sensing the conducting condition and then serially scanning out the conductive state value of the two-sate element as a binary logic bit). The device provides the functionality of being able to test any on-chip non-memory circuitry that depends on a memory circuit being fully functional and operational while still at the wafer tester and before having to “blow” (i.e., program) any fuses.
摘要翻译：一种集成电路器件，其通过根据串行扫描的编程数据的二进制位编程（即，改变）两状态元件的导通状态来消除双状态元件（例如，线熔丝或反熔丝）的激光编程此后，器件可以通过感测导通条件来验证双态元件的实际编程，然后串行扫描两元件的导通状态值作为二进制逻辑位）。该器件提供了能够测试任何片上非存储器电路的功能，该片上非存储器电路取决于完全功能和可操作的存储器电路，同时仍然在晶片测试器处，并且在必须“吹”（即编程）任何保险丝之前。

4. 发明授权

US06346846B1 Methods and apparatus for blowing and sensing antifuses 失效
标题翻译：用于吹制和检测反熔丝的方法和装置
公开(公告)号：US06346846B1
公开(公告)日：2002-02-12
申请号：US09466479
申请日：1999-12-17
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
IPC分类号： H01H3776
CPC分类号： G11C5/145 , G11C17/18
摘要： Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.
摘要翻译：提供了用于吹制和检测反熔丝的方法和装置。具体地，在第一方面中，提供一种通过选择一组反熔丝中的一个并且施加高电压来改变所选择的反熔丝的状态来改变多个反熔丝之一的状态的方法。在第二和第三方面中，提供了用于执行第一方面的方法的装置。在第四方面，提供了一种用于升压电压的方法，包括以下步骤：在第一级升压电路的第一级存储机构内产生第一电压，产生等于第一级升压电路中第一电压的大约两倍的第二电压，第二级升压电路的第二级第二级存储机构，并且基于第二级升压电路的第二电压产生约三倍的第一电压。在第五方面中，提供了用于执行第四方面的方法的装置。

5. 发明授权

US06452439B1 Inductive voltage spike generator with diode shunt 失效
标题翻译：具有二极管分流的感应电压尖峰发生器
公开(公告)号：US06452439B1
公开(公告)日：2002-09-17
申请号：US09850353
申请日：2001-05-07
申请人： John A. Fifield , Nicholas M. Van heel
发明人： John A. Fifield , Nicholas M. Van heel
IPC分类号： G05F110
CPC分类号： H01L23/62 , H01L23/5256 , H01L23/58 , H01L2224/48091 , H01L2224/49171 , H01L2924/30107 , H02M3/155 , H01L2924/00014 , H01L2924/00
摘要： A voltage generator for an integrated circuit chip comprises an integrated circuit chip with a power supply having a voltage available to the chip; an inductor on or in contact with the integrated circuit chip electrically connected to the power supply through which current is driven; and a clock adapted to interrupting current flowing from the power supply through the inductor at desired time intervals to create voltage spikes above the power supply voltage. The inductor may comprise a portion of the lead frame connecting the integrated circuit chip to an integrated chip package. The voltage spikes generate a voltage about two or more times the voltage of the power supply available to the chip. Where the integrated circuit chip includes an electrical fuse and/or a battery, the fuse on the chip may be adapted to be programmed or the battery charged by the voltage spikes.
摘要翻译：一种用于集成电路芯片的电压发生器包括具有电源可用于芯片的电源的集成电路芯片; 与集成电路芯片接触或接触的电感器，其电连接到通过其驱动电流的电源; 以及适于以期望的时间间隔中断从电源流过电感器的电流以在电源电压之上产生电压尖峰的时钟。电感器可以包括将集成电路芯片连接到集成芯片封装的引线框架的一部分。电压尖峰产生大约是芯片可用电源电压的两倍或更多倍的电压。在集成电路芯片包括电熔丝和/或电池的情况下，芯片上的保险丝可能被编程或由电压尖峰充电的电池。

6. 发明授权

US06384666B1 Antifuse latch device with controlled current programming and variable trip point 有权
标题翻译：具有受控电流编程和可变跳变点的防漏锁存器件
公开(公告)号：US06384666B1
公开(公告)日：2002-05-07
申请号：US09816030
申请日：2001-03-23
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Nicholas M. van Heel
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Nicholas M. van Heel
IPC分类号： H01H3776
CPC分类号： G11C17/18
摘要： A latch device is provided having a variable resistive trip point and controlled current programming. The latch device has a trip point current control element that controls an amount of current passing from a voltage source into the latch circuit, thereby varying the resistive trip point of the latch device. The latch device also has a programming current control element that controls an amount of programming current passing through the fuse element during programming. The trip point current reference and a programming current reference are provided by reference circuits having a plurality of selectable inputs that operate to change the current references binarily. An integrated circuit is also provided in which a plurality of the fuse latch devices are connected together in parallel such that the same trip point current reference and programming current reference are supplied to each latch device.
摘要翻译：提供具有可变电阻跳变点和受控电流编程的锁存器件。闩锁装置具有跳闸电流控制元件，其控制从电压源流入锁存电路的电流量，从而改变闩锁装置的电阻性跳变点。闩锁装置还具有编程电流控制元件，其控制在编程期间通过熔丝元件的编程电流量。跳变点电流基准和编程电流基准由具有多个可选择输入的参考电路提供，所述多个可选输入用于二次改变当前基准。还提供一种集成电路，其中多个熔丝锁存器件并联连接在一起，使得相同的跳变点电流参考和编程电流基准被提供给每个锁存器件。

7. 发明授权

US06348827B1 Programmable delay element and synchronous DRAM using the same 失效
标题翻译：可编程延迟元件和同步DRAM
公开(公告)号：US06348827B1
公开(公告)日：2002-02-19
申请号：US09501216
申请日：2000-02-10
申请人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
发明人： John A. Fifield , Nicholas M. van Heel , Mark D. Jacunski , David E. Chapman , David E. Douse
IPC分类号： H03H1126
CPC分类号： G11C7/222 , G11C7/04 , G11C7/1072 , H03K5/133 , H03K2005/00065
摘要： A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.
摘要翻译：可编程延迟元件包括电流源场效应晶体管（FET），开关器件，预充电器件和逆变器器件。电流源FET栅极可编程，预定量的电流。耦合到电流源FET的开关器件接收具有第一和第二电压电平的输入信号。当输入信号处于第二电压电平时，预充电装置对耦合到电流源FET的漏极的节点进行预充电。还耦合到电流源FET的漏极的逆变器装置在输入信号处于第一电压电平时输出延迟信号，延迟信号由可编程预定量的电流定义。逆变器装置产生基本上与参数灵敏度（例如温度变化）无关的逆变器开关点。此外，电流源FET相对于本发明的开关器件的放置允许可编程延迟元件快速达到线性和可预测的操作状态。

8. 发明授权

US08724365B2 Programmable semiconductor device 有权
标题翻译：可编程半导体器件
公开(公告)号：US08724365B2
公开(公告)日：2014-05-13
申请号：US13427162
申请日：2012-03-22
申请人： William R. Tonti , Wayne S. Berry , John A. Fifield , William H. Guthrie , Richard S. Kontra
发明人： William R. Tonti , Wayne S. Berry , John A. Fifield , William H. Guthrie , Richard S. Kontra
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译：可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。

9. 发明申请

US20140003164A1 MEMORY ARRAY WITH ON AND OFF-STATE WORDLINE VOLTAGES HAVING DIFFERENT TEMPERATURE COEFFICIENTS 有权
标题翻译：具有开启和关闭状态的存储器阵列具有不同温度系数的字线电压
公开(公告)号：US20140003164A1
公开(公告)日：2014-01-02
申请号：US13534096
申请日：2012-06-27
申请人： John A. Fifield , Mark D. Jacunski
发明人： John A. Fifield , Mark D. Jacunski
IPC分类号： G11C5/14 , H02J1/10 , G11C8/08
CPC分类号： G11C8/08 , G11C7/04 , G11C11/4085 , Y10T307/555
摘要： Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.
摘要翻译：公开了一种存储器阵列结构，其中字线驱动器选择性地将高导通状态电压（VWLH）或低关态电压（VWLL）施加到字线。 VWLH具有轻微的负温度系数，使得其受到栅极介电可靠性限制允许的高度调节，而VWLL具有基本上中性的温度系数。为了实现这一点，字线驱动器耦合到一个或多个电压调节电路。在一个实施例中，字线驱动器耦合到单个电压调节电路，其包括具有输出多个参考电压的单个输出级的单个电压参考电路。还公开了一种电压参考电路，其可以结合到如所描述的存储器阵列结构的电压调节电路中，或者可以并入任何其它需要具有不同温度系数的电压的集成电路结构。还公开了一种操作存储器阵列结构的方法。

10. 发明授权

US08027207B2 Leakage compensated reference voltage generation system 有权
标题翻译：泄漏补偿参考电压发生系统
公开(公告)号：US08027207B2
公开(公告)日：2011-09-27
申请号：US12639454
申请日：2009-12-16
申请人： John A. Fifield , Harold Pilo
发明人： John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C17/16 , G11C5/147 , G11C7/062 , G11C7/12 , G11C17/18 , G11C29/02 , G11C29/021 , G11C29/028
摘要： An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to the selected bitline pull-up resistor. As the sensing trip point is adjusted by selection of a bitline pull-up resistor, a pair of pull-up and pull-down resistors are adjusted together to adjust the impedance of the reference voltage generator. A leakage-path simulation structure including a parallel connection of bitcells is added to the reference voltage generator. The leakage-path simulation structure imitates the bitcells on a bitline in the array of e-fuses. Leakage current on the bitline offsets the bitline voltage by a certain error voltage. The reference voltage is also offset by a fraction of the error voltage to balance the shifts in the ‘1’ and ‘0’ margin levels in the presence of leakage.
摘要翻译：电熔丝感测电路采用单端感测方案，其中参考电压被补偿以进行泄漏。参考电压发生器包括与所选位线上拉电阻相似的上拉电阻。由于通过选择位线上拉电阻来调整感测跳变点，一对上拉电阻和下拉电阻一起调节，以调整参考电压发生器的阻抗。包括比特单元的并联连接的泄漏路径模拟结构被添加到参考电压发生器。泄漏路径模拟结构模仿电子熔丝阵列中的位线上的位单元。位线上的漏电流将位线电压抵消一定的误差电压。在存在泄漏的情况下，参考电压也被误差电压的一部分偏移以平衡'1'和'0'余量水平的偏移。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式