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1. 发明授权

US07085971B2 ECC based system and method for repairing failed memory elements 失效
标题翻译：基于ECC的系统和修复失败的内存元素的方法
公开(公告)号：US07085971B2
公开(公告)日：2006-08-01
申请号：US10035474
申请日：2001-10-25
申请人： John E. Barth, Jr. , Wayne F. Ellis , John A. Fifield
发明人： John E. Barth, Jr. , Wayne F. Ellis , John A. Fifield
IPC分类号： G11C29/00
CPC分类号： G11C29/72 , G11C29/42 , G11C29/789 , G11C2029/4402
摘要： An ECC based system and method within an integrated circuit memory for self-repair of a failed memory element is disclosed. The method includes processing, within the integrated circuit, data and check bits retrieved from addressed memory locations therein. The locations of memory failures are automatically recorded within the integrated circuit. Logic circuits within the integrated circuit automatically identify failure patterns based on the locations. Based on the identified failure patterns, logic circuits within the integrated circuit then permanently replace a failed memory element with an appropriate redundancy element, using devices such as electronic fuse or antifuse. In this manner, the integrated circuit automatically identifies and effects self repair of a failed memory element therein.
摘要翻译：公开了一种用于故障存储器元件的自修复的集成电路存储器内的基于ECC的系统和方法。该方法包括在集成电路内处理从其中的寻址的存储器位置检索的数据和校验位的处理。内存故障的位置会自动记录在集成电路中。集成电路内的逻辑电路根据位置自动识别故障模式。基于所识别的故障模式，集成电路内的逻辑电路然后使用诸如电子熔断器或反熔丝的装置用适当的冗余元件永久地替换故障存储器元件。以这种方式，集成电路自动识别并实现其中的故障存储元件的自身修复。

2. 发明授权

US07193262B2 Low-cost deep trench decoupling capacitor device and process of manufacture 有权
标题翻译：低成本深沟槽去耦电容器件及其制造工艺
公开(公告)号：US07193262B2
公开(公告)日：2007-03-20
申请号：US10905094
申请日：2004-12-15
申请人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
发明人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L27/0805 , H01L29/66181 , H01L29/945
摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
摘要翻译：一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

3. 发明授权

US5134616A Dynamic RAM with on-chip ECC and optimized bit and word redundancy 失效
标题翻译：具有片上ECC和优化位和动态冗余的动态RAM
公开(公告)号：US5134616A
公开(公告)日：1992-07-28
申请号：US479145
申请日：1990-02-13
申请人： John E. Barth, Jr. , Charles E. Drake , John A. Fifield , William P. Hovis , Howard L. Kalter , Scott C. Lewis , Daniel J. Nickel , Charles H. Stapper , James A. Yankosky
发明人： John E. Barth, Jr. , Charles E. Drake , John A. Fifield , William P. Hovis , Howard L. Kalter , Scott C. Lewis , Daniel J. Nickel , Charles H. Stapper , James A. Yankosky
IPC分类号： G11C11/401 , G06F11/10 , G11C29/00 , G11C29/42
CPC分类号： G11C29/84 , G06F11/1008
摘要： A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed. At the same time, having a set of interrelated bits in the SRAM compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

4. 发明授权

US08937345B2 Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact 有权
标题翻译：集成电路包括通过上覆触点与沟槽电容器电连接的有源晶体管
公开(公告)号：US08937345B2
公开(公告)日：2015-01-20
申请号：US13454635
申请日：2012-04-24
申请人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
发明人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
IPC分类号： H01L27/108 , H01L21/768 , H01L23/485
CPC分类号： H01L21/76895 , H01L23/485 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.
摘要翻译：集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器有源晶体管。

5. 发明授权

US08263472B2 Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 失效
标题翻译：用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管
公开(公告)号：US08263472B2
公开(公告)日：2012-09-11
申请号：US13324486
申请日：2011-12-13
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L21/76
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层，第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

6. 发明授权

US08097525B2 Vertical through-silicon via for a semiconductor structure 有权
标题翻译：用于半导体结构的垂直通硅硅通孔
公开(公告)号：US08097525B2
公开(公告)日：2012-01-17
申请号：US12201580
申请日：2008-08-29
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L21/00
CPC分类号： H01L23/481 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.
摘要翻译：半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

7. 发明授权

US07668003B2 Dynamic random access memory circuit, design structure and method 有权
标题翻译：动态随机存取电路，设计结构与方法
公开(公告)号：US07668003B2
公开(公告)日：2010-02-23
申请号：US12108548
申请日：2008-04-24
申请人： John E. Barth, Jr. , Kangguo Cheng , Hoki Kim , Geng Wang
发明人： John E. Barth, Jr. , Kangguo Cheng , Hoki Kim , Geng Wang
IPC分类号： G11C11/24
CPC分类号： H01L27/10829 , G11C7/02 , G11C11/4099 , H01L27/10861 , H01L27/10885 , H01L27/10891 , H01L27/10897
摘要： Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.
摘要翻译：公开了一种DRAM电路，其包含改进的参考单元，具有存储单元的一半电容，不需要特定参考电压，并且可以使用与存储单元相同的制造工艺来形成。该DRAM电路包括具有单沟槽电容器的存储单元和具有两个沟槽电容器的参考单元。两个参考单元沟槽电容器通过合并的埋入式电容器板串联连接，使得它们提供存储单元沟槽电容器的一半的电容。此外，参考单元沟槽电容器具有与存储单元沟槽电容器基本相同的结构，使得它们可以与存储单元沟槽电容器结合形成。还公开了用于上述存储电路的设计结构和用于形成上述存储电路的方法。

8. 发明申请

US20090129192A1 DESIGN STRUCTURE FOR LOW OVERHEAD SWITCHED HEADER POWER SAVINGS APPARATUS 失效
标题翻译：低开关开关电源节省设备的设计结构
公开(公告)号：US20090129192A1
公开(公告)日：2009-05-21
申请号：US12116322
申请日：2008-05-07
申请人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
发明人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C8/08 , G11C5/147 , G11C5/148 , G11C8/12
摘要： A design structure embodied in a machine readable medium used in a design process includes a tri-state power gating apparatus for reducing leakage current in a memory array. The apparatus includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and a header driver operatively coupled to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构包括用于减少存储器阵列中的漏电流的三态电源门控装置。所述装置包括耦合到所述存储器阵列的第一分配报头装置，所述第一分配报头装置被配置为限制通过所述存储器阵列的泄漏电流; 以及头部驱动器，其可操作地耦合到所述第一分配报头装置，用于实现所述第一分配报头装置的三态操作，其中三态操作包括睡眠模式，唤醒模式和保持模式。

9. 发明授权

US07400546B1 Low overhead switched header power savings apparatus 失效
标题翻译：低开销交换机头节能设备
公开(公告)号：US07400546B1
公开(公告)日：2008-07-15
申请号：US11940642
申请日：2007-11-15
申请人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
发明人： John E. Barth, Jr. , Harold Pilo , Vinod Ramadurai
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C8/12
摘要： A tri-state power gating apparatus for reducing leakage current in a memory array includes a first distributed header device coupled to the memory array, the first distributed header device is configured for limiting leakage current through the memory array; and a header driver operatively coupled to the first distributed header device for enabling tri-state operation of the first distributed header device, wherein tri-state operation includes sleep mode, wake mode, and retention mode.
摘要翻译：用于减少存储器阵列中的漏电流的三态电源门控装置包括耦合到存储器阵列的第一分布式头部装置，第一分配头部装置被配置为限制通过存储器阵列的漏电流; 以及头部驱动器，其可操作地耦合到所述第一分配报头装置，用于实现所述第一分配报头装置的三态操作，其中三态操作包括睡眠模式，唤醒模式和保持模式。

10. 发明授权

US07089136B2 Method for reduced electrical fusing time 失效
标题翻译：降低电熔时间的方法
公开(公告)号：US07089136B2
公开(公告)日：2006-08-08
申请号：US10604414
申请日：2003-07-18
申请人： Darren L. Anand , John E. Barth, Jr. , Steven F. Oakland , Michael R. Ouellette
发明人： Darren L. Anand , John E. Barth, Jr. , Steven F. Oakland , Michael R. Ouellette
IPC分类号： G01R31/00
CPC分类号： G11C17/16 , G11C17/18
摘要： An electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output of the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain when the next fuse(s) is not to be blown. Accordingly, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.
摘要翻译：一种电熔丝回路设计，用于减少用冗余eFuse电路制造的半导体器件的测试时间。除了熔丝锁存器和图案锁存器之外，每个eFuse电路还提供一对二路复用器（MUX）。保险丝图案锁存器中存储有要熔断保险丝的信息。模式锁存器的输出与程序输入进行“与”运算以提供MUX的选择信号。基于选择信号，MUX允许移位的“1”进入移位链中的下一个锁存器，或者在下一个保险丝不被熔断时，旁路下一个锁存器或锁存在换档链中。因此，本发明仅能够使与熔断器相关联的熔丝锁存器保持被转换的“1”传播到下一个eFuse电路。

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