专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5993170A Apparatus and method for compressing high purity gas 失效
标题翻译：用于压缩高纯度气体的装置和方法
公开(公告)号：US5993170A
公开(公告)日：1999-11-30
申请号：US57518
申请日：1998-04-09
申请人： Joe Stevens , Allen Thompson , Norman Cowan , David Alvarez
发明人： Joe Stevens , Allen Thompson , Norman Cowan , David Alvarez
IPC分类号： F04B35/00 , F04B39/00 , F04B39/04 , H05B1/00
CPC分类号： F04B35/008 , F04B39/0005 , F04B39/04
摘要： An improved method and apparatus are disclosed for isolating product gas from compressor operating fluid. A portion of a piston rod directly exposed to the compressor's operating fluid (the oily portion of the piston rod) is atmospherically isolated from the remaining portion of the piston rod by providing the piston rod with a collar that separates the oily portion of the piston rod from the remainder of the piston rod. A first and a second flexible membrane are coupled to the collar to form a first isolation region, and a second isolation region; the first isolation region encases the oily portion of the piston rod and atmospherically isolates it from the second isolation region, and the second isolation region provides additional isolation from both the operating fluid and the ambient environment. A higher pressure is maintained along the backside of the piston that compresses the product gas than the pressure within the adjacent isolation region. Pairs of wipers with vents coupled therebetween additionally may be employed to further improve product gas isolation.
摘要翻译：公开了一种改进的方法和装置，用于从压缩机工作流体中分离产物气体。直接暴露于压缩机的工作流体（活塞杆的油性部分）的活塞杆的一部分与活塞杆的剩余部分大气隔离，为活塞杆提供一个将活塞杆的油性部分分开的套环从活塞杆的其余部分。第一和第二柔性膜耦合到套环以形成第一隔离区域和第二隔离区域; 第一隔离区域包围活塞杆的油性部分并使其与第二隔离区域大气隔离，并且第二隔离区域提供与工作流体和周围环境的额外隔离。沿着活塞的背面保持较高的压力，其压缩产品气体而不是相邻隔离区域内的压力。可以采用具有连接在其上的通风口的擦拭器对以进一步改善产品气体隔离。

2. 发明授权

US07732834B2 Semiconductor ESD device and method of making same 有权
标题翻译：半导体ESD器件及其制造方法
公开(公告)号：US07732834B2
公开(公告)日：2010-06-08
申请号：US11698674
申请日：2007-01-26
申请人： Cornelius Christian Russ , Kai Esmark , David Alvarez , Jens Schneider
发明人： Cornelius Christian Russ , Kai Esmark , David Alvarez , Jens Schneider
IPC分类号： H01L29/74
CPC分类号： H01L29/735 , H01L27/0262 , H01L29/0615 , H01L29/0619 , H01L29/0692 , H01L29/41708 , H01L29/456 , H01L29/732 , H01L29/7436
摘要： A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.
摘要翻译：半导体器件包括设置在第一半导体类型的半导体本体内的ESD器件区域，围绕ESD器件区域的隔离区域，设置在ESD区域内的半导体本体的表面处的第二导电类型的第一掺杂区域，以及设置在ESD区域内的半导体本体与第一掺杂区域的至少一部分之间的第一导电类型的第二掺杂区域，其中第二掺杂区域的掺杂浓度高于半导体本体。第二半导体类型的第三掺杂区域设置在半导体本体上，并且第一导电类型的第四区域设置在第三掺杂区域上。第二导电类型的第五掺杂区域设置在半导体本体上。触发装置和SCR由其形成。

3. 发明申请

US20100006944A1 MIXED VOLTAGE TOLERANT INPUT/OUTPUT ELECTROSTATIC DISCHARGE DEVICES 有权
标题翻译：混合电压输入/输出静电放电装置
公开(公告)号：US20100006944A1
公开(公告)日：2010-01-14
申请号：US12168936
申请日：2008-07-08
申请人： Kiran V. Chatty , David Alvarez , Bong Jae Kwon , Christian C. Russ
发明人： Kiran V. Chatty , David Alvarez , Bong Jae Kwon , Christian C. Russ
IPC分类号： H01L21/8249 , H01L27/06
CPC分类号： H01L27/0259 , H01L27/0266
摘要： An input/output (I/O) mixed-voltage drive circuit and electrostatic discharge protection device for coupling to an I/O pad. The device includes an NFET device having a gate, a drain, a source and body, the gate adapted for coupling to a pre-drive circuit, the source and the body being coupled to one another and to ground. The device also includes a bipolar junction transistor having a collector, an emitter and a base, the emitter being coupled to the drain of the NFET and the collector being coupled to the I/O pad.
摘要翻译：用于耦合到I / O焊盘的输入/输出（I / O）混合电压驱动电路和静电放电保护装置。该器件包括具有栅极，漏极，源极和主体的NFET器件，栅极适用于耦合到预驱动电路，源极和主体被耦合到彼此并接地。器件还包括具有集电极，发射极和基极的双极结型晶体管，发射极耦合到NFET的漏极，并且集电极耦合到I / O焊盘。

4. 发明申请

US20090189194A1 Electrostatic Discharge (ESD) Protection Circuit Placement in Semiconductor Devices 有权
标题翻译：半导体器件中的静电放电（ESD）保护电路放置
公开(公告)号：US20090189194A1
公开(公告)日：2009-07-30
申请号：US12021123
申请日：2008-01-28
申请人： Uwe Paul Schroeder , David Alvarez
发明人： Uwe Paul Schroeder , David Alvarez
IPC分类号： H01L27/10 , G06F17/50 , H01L21/82
CPC分类号： H01L27/0207 , G06F17/5072 , H01L27/0248 , H01L27/0296
摘要： Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one electrostatic discharge (ESD) protection circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.
摘要翻译：公开了半导体器件，其制造方法，以及集成电路的电路部件的配置方法。在一个实施例中，半导体器件包括以多行布置的多个器件的阵列。至少一个静电放电（ESD）保护电路或其一部分设置在多个器件的阵列的多行中的至少一个中。

5. 发明申请

US20080142849A1 Semiconductor ESD device and method of making same 有权
标题翻译：半导体ESD器件及其制造方法
公开(公告)号：US20080142849A1
公开(公告)日：2008-06-19
申请号：US11638067
申请日：2006-12-13
申请人： David Alvarez , Richard Lindsay , Manfred Eller , Cornelius Christian Russ
发明人： David Alvarez , Richard Lindsay , Manfred Eller , Cornelius Christian Russ
IPC分类号： H01L29/76
CPC分类号： H01L21/26513 , H01L27/027 , H01L29/0619 , H01L29/665 , H01L29/7833
摘要： An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first edge of the gate, wherein the first source/drain region is doped with a dopant of a second conductivity type opposite the first conductivity type, and at least a portion of the first source/drain region is doped with a dopant of the first conductivity type. The concentration of the second conductivity type dopant exceeds the concentration of the first conductivity type dopant, and the concentration of the first conductivity type dopant in the first source/drain exceeds the first concentration. A second source/drain region is also formed at the upper surface of the semiconductor body adjacent to a second edge of the gate, wherein the second source/drain region is doped with a dopant of the second conductivity type.
摘要翻译： ESD保护器件包括半导体本体，形成在半导体本体中的沟道上的栅极，该沟道掺杂有第一导电类型的掺杂剂的第一浓度。第一源极/漏极区域形成在与栅极的第一边缘相邻的半导体本体的表面上，其中第一源极/漏极区域掺杂有与第一导电类型相反的第二导电类型的掺杂物，并且至少第一源/漏区的一部分掺杂有第一导电类型的掺杂剂。第二导电型掺杂物的浓度超过第一导电型掺杂剂的浓度，并且第一源极/漏极中的第一导电类型掺杂剂的浓度超过第一浓度。第二源极/漏极区域还形成在与栅极的第二边缘相邻的半导体本体的上表面处，其中第二源极/漏极区域掺杂有第二导电类型的掺杂物。

6. 发明申请

US20070210387A1 ESD protection device and method 有权
标题翻译： ESD保护装置及方法
公开(公告)号：US20070210387A1
公开(公告)日：2007-09-13
申请号：US11370369
申请日：2006-03-08
申请人： Cornelius Russ , David Alvarez , Kiran Chatty , Jens Schneider , Robert Gauthier , Martin Wendel
发明人： Cornelius Russ , David Alvarez , Kiran Chatty , Jens Schneider , Robert Gauthier , Martin Wendel
IPC分类号： H01L23/62
CPC分类号： H01L29/78 , H01L29/0626 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/1087 , H01L29/456
摘要： An ESD protection device includes a source region, a channel region adjacent the source region, and an elongated drain region spaced from the source region by the channel region. The elongated drain region includes an unsilicided portion adjacent the channel and a silicided portion spaced from channel region by the unsilicided portion. A first ESD region is located beneath the silicided portion of the elongated drain region and a second ESD region is located beneath the unsilicided portion of the elongated drain region, the second ESD region being spaced from the first ESD region.
摘要翻译： ESD保护器件包括源极区域，与源极区域相邻的沟道区域以及由沟道区域与源极区域间隔开的细长漏极区域。细长的漏极区域包括邻近通道的非硅化部分和通过非硅化部分与沟道区域隔开的硅化部分。第一ESD区域位于细长漏区域的硅化部分下方，第二ESD区域位于细长漏区域的未硅化部分的下方，第二ESD区域与第一ESD区域间隔开。

7. 发明授权

US08315024B2 Electrostatic discharge protection circuit, integrated circuit and method of protecting circuitry from an electrostatic discharge voltage 有权
标题翻译：静电放电保护电路，集成电路和保护电路免受静电放电电压的影响
公开(公告)号：US08315024B2
公开(公告)日：2012-11-20
申请号：US12560475
申请日：2009-09-16
申请人： Christian Russ , Wolfgang Soldner , Gernot Langguth , David Alvarez , Krysztof Domanski
发明人： Christian Russ , Wolfgang Soldner , Gernot Langguth , David Alvarez , Krysztof Domanski
IPC分类号： H02H3/22
CPC分类号： H01L27/0281 , H01L27/0285
摘要： Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node.
摘要翻译：本文给出了包括静电放电（ESD）保护电路的实现。 ESD保护电路包括第一晶体管和第二晶体管。第一晶体管具有耦合到第一电源线的第一端子和耦合到第二电源线的本体。第二晶体管具有耦合到第二电源线的第一端子，耦合到第一电源线的体和耦合到第一晶体管的第二端子以限定受保护节点的第二端子。 ESD保护电路还包括具有耦合到受保护节点的第一端子的限流元件。

8. 发明授权

US08247845B2 Electrostatic discharge (ESD) protection circuit placement in semiconductor devices 有权
标题翻译：半导体器件中的静电放电（ESD）保护电路放置
公开(公告)号：US08247845B2
公开(公告)日：2012-08-21
申请号：US12021123
申请日：2008-01-28
申请人： Uwe Paul Schroeder , David Alvarez
发明人： Uwe Paul Schroeder , David Alvarez
IPC分类号： H01L27/06
CPC分类号： H01L27/0207 , G06F17/5072 , H01L27/0248 , H01L27/0296
摘要： Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one electrostatic discharge (ESD) protection circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.
摘要翻译：公开了半导体器件，其制造方法，以及集成电路的电路部件的配置方法。在一个实施例中，半导体器件包括以多行布置的多个器件的阵列。至少一个静电放电（ESD）保护电路或其一部分设置在多个器件的阵列的多行中的至少一个中。

9. 发明申请

US20120176710A1 Semiconductor ESD Circuit and Method 有权
标题翻译：半导体ESD电路及方法
公开(公告)号：US20120176710A1
公开(公告)日：2012-07-12
申请号：US12987658
申请日：2011-01-10
申请人： Krzysztof Domanski , Wolfgang Soldner , Cornelius Christian Russ , David Alvarez , Adrien Ille
发明人： Krzysztof Domanski , Wolfgang Soldner , Cornelius Christian Russ , David Alvarez , Adrien Ille
IPC分类号： H02H9/00 , H01L29/78
CPC分类号： H02H9/046 , H01L27/0285 , H01L29/0692 , H01L29/1083
摘要： In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
摘要翻译：在一个实施例中，用于在第一节点和第二节点之间提供保护的静电放电（ESD）电路包括具有耦合到第一节点的第一源极/漏极和耦合到中间节点的第二源极/漏极的第一MOS器件。 ESD电路还包括耦合在第一MOS器件的栅极和第一节点之间的第一电容器，耦合在第一MOS器件的中间节点的栅极之间的第一电阻器，第二MOS / 中间节点和耦合到第二节点的第二源极/漏极，耦合在第二MOS器件的栅极和第一节点之间的第二电容器，以及耦合在第二MOS器件的栅极和第二节点之间的第二电阻器。

10. 发明申请

US20120099229A1 Semiconductor ESD Device and Method 有权
标题翻译：半导体ESD器件及方法
公开(公告)号：US20120099229A1
公开(公告)日：2012-04-26
申请号：US12911582
申请日：2010-10-25
申请人： Krzysztof Domanski , Cornelius Christian Russ , David Alvarez , Wolfgang Soldner
发明人： Krzysztof Domanski , Cornelius Christian Russ , David Alvarez , Wolfgang Soldner
IPC分类号： H02H9/04 , H01L29/73
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier.
摘要翻译：实施例半导体器件具有设置在设置在半导体本体内的ESD器件区域内的第二器件区域上的第一器件区域。还包括设置在第二器件区域上的第三器件区域，与第二器件区域相邻的第四器件区域，设置在第四器件区域内的第五器件区域以及与第四器件区域相邻的第六器件区域。第一和第四区域具有第一半导体类型，并且第二，第三，第五和第六区域具有与第一导电类型相反的第二导电类型。第四器件区域和第六器件区域之间的界面形成二极管结。第一，第二，第四和第五器件区域形成可控硅整流器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式