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1. 发明授权

US07709896B2 ESD protection device and method 有权
标题翻译： ESD保护装置及方法
公开(公告)号：US07709896B2
公开(公告)日：2010-05-04
申请号：US11370369
申请日：2006-03-08
申请人： Cornelius Christian Russ , David Alvarez , Kiran V. Chatty , Jens Schneider , Robert Gauthier , Martin Wendel
发明人： Cornelius Christian Russ , David Alvarez , Kiran V. Chatty , Jens Schneider , Robert Gauthier , Martin Wendel
IPC分类号： H01L23/62
CPC分类号： H01L29/78 , H01L29/0626 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/1087 , H01L29/456
摘要： An ESD protection device includes a source region, a channel region adjacent the source region, and an elongated drain region spaced from the source region by the channel region. The elongated drain region includes an unsilicided portion adjacent the channel and a silicided portion spaced from channel region by the unsilicided portion. A first ESD region is located beneath the silicided portion of the elongated drain region and a second ESD region is located beneath the unsilicided portion of the elongated drain region, the second ESD region being spaced from the first ESD region.
摘要翻译： ESD保护器件包括源极区域，与源极区域相邻的沟道区域以及由沟道区域与源极区域间隔开的细长漏极区域。细长的漏极区域包括邻近通道的非硅化部分和通过非硅化部分与沟道区域隔开的硅化部分。第一ESD区域位于细长漏区域的硅化部分下方，第二ESD区域位于细长漏区域的未硅化部分的下方，第二ESD区域与第一ESD区域间隔开。

2. 发明申请

US20070284659A1 METHOD OF FORMING HIGH VOLTAGE N-LDMOS TRANSISTORS HAVING SHALLOW TRENCH ISOLATION REGION WITH DRAIN EXTENSIONS 审中-公开
标题翻译：形成具有泄漏扩展的浅层分离区域的高电压N-LDMOS晶体管的方法
公开(公告)号：US20070284659A1
公开(公告)日：2007-12-13
申请号：US11844573
申请日：2007-08-24
申请人： Wagdi Abadeer , Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L21/26586 , H01L21/266 , H01L29/0653 , H01L29/086 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.
摘要翻译：公开了一种用于晶体管的方法和结构，该晶体管具有栅极，栅极下方的沟道区，沟道区一侧的源极区，与源极区沟道区相反侧的漏极区，浅沟槽在漏极区和沟道区之间的衬底中的隔离（STI）区，以及在STI区之下的漏极延伸。漏极延伸沿着STI区域的底部并沿着STI的边的一部分定位。沿着STI底部的漏极延伸部分可以包括不同于沿着STI侧面的漏极延伸部分的掺杂剂注入。沿着STI侧面的排水延伸部分从STI的底部延伸到部分沿着STI侧面的位置。 STI区域位于栅极的一部分之下。漏极延伸部在漏极区域和围绕STI的下周边的沟道区域之间提供导电路径。漏极区域比源极区域更靠近栅极定位。

3. 发明申请

US20070253126A1 SUBSTRATE TRIGGERING FOR ESD PROTECTION IN SOI 有权
标题翻译： SOI中ESD保护的衬底触发
公开(公告)号：US20070253126A1
公开(公告)日：2007-11-01
申请号：US11380525
申请日：2006-04-27
申请人： Robert Gauthier, Jr. , Junjun Li , Souvick Mitra , Christopher Putnam
发明人： Robert Gauthier, Jr. , Junjun Li , Souvick Mitra , Christopher Putnam
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： Electrostatic discharge (ESD) protection device and process for protecting a conventional FET. The device includes at least one FET body forming a resistance, and a triggering circuit coupled to a protection FET and the resistance. The resistance raises a voltage of the at least one body, such that the protection FET is triggered at a voltage lower than the conventional FET.
摘要翻译：静电放电（ESD）保护装置和保护常规FET的工艺。该器件包括至少一个形成电阻的FET体，以及耦合到保护FET和电阻的触发电路。电阻提高至少一个体的电压，使得保护FET在比常规FET低的电压下被触发。

4. 发明申请

US20070023866A1 VERTICAL SILICON CONTROLLED RECTIFIER ELECTRO-STATIC DISCHARGE PROTECTION DEVICE IN BI-CMOS TECHNOLOGY 审中-公开
标题翻译： BI-CMOS技术中的垂直硅控制整流器电子放电保护装置
公开(公告)号：US20070023866A1
公开(公告)日：2007-02-01
申请号：US11161230
申请日：2005-07-27
申请人： Kiran Chatty , Robert Gauthier , Andreas Stricker , Min Woo
发明人： Kiran Chatty , Robert Gauthier , Andreas Stricker , Min Woo
IPC分类号： H01L27/082
CPC分类号： H01L27/0262 , H01L29/732
摘要： A vertical silicon controlled rectifier (SCR) that directs an electro-static discharge (ESD) current directly to ground from the input/output pad. The vertical SCR is includes a vertical NPN and a vertical PNP that creates a very good SCR exhibiting very low ohmic on-resistance. The vertical SCR provides a low on-resistance and fast turn on, and can be adjusted to alter the trigger voltage value, holding voltage and how it is triggered. It can be optimized to trigger under ESD events and discharge the ESD current effectively to ground.
摘要翻译：将静电放电（ESD）电流从输入/输出焊盘直接引导到地的垂直可控硅整流器（SCR）。垂直SCR包括垂直NPN和垂直PNP，其产生非常好的SCR，表现出非常低的欧姆导通电阻。垂直SCR提供低导通电阻和快速导通，可以调整以改变触发电压值，保持电压以及如何触发。它可以优化以在ESD事件下触发并将ESD电流有效地放电到地。

5. 发明申请

US20060226491A1 INVERTED MULTILAYER SEMICONDUCTOR DEVICE ASSEMBLY 失效
标题翻译：反相多层半导体器件组件
公开(公告)号：US20060226491A1
公开(公告)日：2006-10-12
申请号：US10907566
申请日：2005-04-06
申请人： Robert Gauthier , Mahmoud Mousa , Christopher Putnam
发明人： Robert Gauthier , Mahmoud Mousa , Christopher Putnam
IPC分类号： H01L29/04 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/76251 , H01L21/8221 , H01L21/823807 , H01L21/84 , H01L27/0688
摘要： An apparatus and method for an inverted multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device may be different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with an active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.
摘要翻译：提供了一种用于倒置多层硅绝缘体（SOI）器件的装置和方法。在多层SOI器件中，器件的至少一个有源区的晶体取向可以不同于至少另一器件的有源区。在多层SOI器件具有包括具有[100]晶体取向的硅有源区的PMOS器件的第一层的情况下，第二层可以是具有晶体取向为[110]的具有硅层的有源区的NMOS器件 ]。第二层结合到第一层。该方法和装置可以扩展到两层以上，从而形成在每层具有不同晶体取向的多层SOI器件。多层SOI器件可形成表面积减小的电路。

6. 发明申请

US20050068702A1 ELECTRO-STATIC DISCHARGE PROTECTION CIRCUIT 有权
标题翻译：电子放电保护电路
公开(公告)号：US20050068702A1
公开(公告)日：2005-03-31
申请号：US10605441
申请日：2003-09-30
申请人： John Connor , Robert Gauthier , Christopher Putnam , Alan Roberts
发明人： John Connor , Robert Gauthier , Christopher Putnam , Alan Roberts
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0285
摘要： An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An ESD protection circuit according to claim 7, wherein said RC network includes one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).
摘要翻译：一种ESD保护电路，包括：一个或多个逆变器（I1，I2，I3），所述一个或多个逆变器中的每一个具有输入和输出; 具有输出节点（RCT）的RC网络（11），与所述一个或多个逆变器中的至少一个的输入端连接的输出节点（RCT）与一个或多个逆变器（I1，I2，I3）中的至少一个的输出端连接的钳位装置（N3）; 以及与RC网络（11）的钳位装置（N3）和输出节点（RCT）通信的反馈装置（NKP）。 8.根据权利要求7所述的ESD保护电路，其中所述RC网络包括一个或多个电阻器和一个或多个去耦电容器。在一个实施例中，反馈装置（NKP）是NFET，并且一个或多个反相器（I1，I2，I3）中的每一个包括PFET和NFET对（P0 / N0，P1 / N1，P2 / N2）。

7. 发明申请

US20050045952A1 PFET-BASED ESD PROTECTION STRATEGY FOR IMPROVED EXTERNAL LATCH-UP ROBUSTNESS 审中-公开
标题翻译：基于PFET的ESD保护策略，用于改进外部锁定稳定性
公开(公告)号：US20050045952A1
公开(公告)日：2005-03-03
申请号：US10604922
申请日：2003-08-27
申请人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
IPC分类号： H01L21/336 , H01L27/02
CPC分类号： H01L27/0266
摘要： A method and apparatus for protection against electrostatic discharge (ESD) with improved latch-up robustness featuring a silicide blocked p-type field effect transistor is disclosed. The transistor has a snapback voltage that is less than the breakdown voltage of its gate oxide. The transistor is part of an integrated circuit and coupled to an I/O pad having no n-diffusions connected directly to it. A given integrated circuit may employ one or more the transistors configured in accordance with the invention that are associated with one or more I/O pads within the integrated circuit.
摘要翻译：公开了一种具有改进的闩锁鲁棒性的防静电放电（ESD）的方法和装置，其具有硅化物阻挡的p型场效应晶体管。晶体管具有小于其栅极氧化物的击穿电压的快速恢复电压。晶体管是集成电路的一部分，并且耦合到没有直接连接到其的n扩散的I / O焊盘。给定的集成电路可以采用根据本发明配置的一个或多个与集成电路内的一个或多个I / O焊盘相关联的晶体管。

8. 发明申请

US20090298957A1 METHOD AND INSTALLATION FOR COMBINED PRODUCTION OF HYDROGEN AND CARBON DIOXIDE 有权
标题翻译：用于二氧化碳和二氧化碳的组合生产的方法和装置
公开(公告)号：US20090298957A1
公开(公告)日：2009-12-03
申请号：US11719248
申请日：2005-10-27
申请人： Pierre-Robert Gauthier , Bernd Polster , Pascal Marty
发明人： Pierre-Robert Gauthier , Bernd Polster , Pascal Marty
IPC分类号： C07C27/06 , B01J7/00
CPC分类号： C01B3/506 , C01B3/48 , C01B3/56 , C01B32/50 , C01B2203/0205 , C01B2203/0283 , C01B2203/046 , C01B2203/047 , C01B2203/0475 , C01B2203/048 , C01B2203/0827 , C01B2203/148 , C01B2203/86 , F25J3/0223 , F25J3/0252 , F25J3/0266 , F25J2200/02 , F25J2200/70 , F25J2205/02 , F25J2205/04 , F25J2205/40 , F25J2205/60 , F25J2210/04 , F25J2215/04 , F25J2220/82 , F25J2230/30 , F25J2245/02 , F25J2245/90 , F25J2270/02 , F25J2270/90 , Y02C10/12 , Y02P20/129 , Y02P20/152 , Y02P30/30
摘要： The invention concerns a method for combined production of hydrogen and carbon dioxide from a mixture of hydrocarbons wherein the residual PSA is treated to produce a carbon dioxide-enriched fluid, and wherein: the residual PSA is compressed to a pressure such that the partial pressure of the CO 2 contained ranges between about 15 and 40 bar; the residue is subjected to one or more condensation/separation steps with production of CO 2 -rich condensate(s) and a purge of noncondensable gas; the purge of noncondensable gas is preferably treated to produce a H 2 -rich permeate which is recycled to the PSA, and a residue which is recycled to syngas generation, Preferably, the condensate(s) are purified by cryogenic distillation to produce food grade CO 2 . The invention also concerns an installation for implementing the method.
摘要翻译：本发明涉及一种从烃混合物中组合生产氢气和二氧化碳的方法，其中残留的PSA被处理以产生富含二氧化碳的流体，并且其中：将残留的PSA压缩至压力使得所含CO 2范围在约15至40巴之间; 残留物经过一个或多个冷凝/分离步骤，产生富CO 2浓缩物和不凝气体的吹扫; 优选处理不凝性气体的吹扫以产生再循环至PSA的富含H 2 O 2的渗透物，以及再循环至合成气产生的残余物。优选地，冷凝物由进行低温蒸馏以产生食品级CO 2。本发明还涉及用于实现该方法的安装。

9. 发明申请

US20080237721A1 STRUCTURE AND CIRCUIT TECHNIQUE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE 有权
标题翻译：具有可调触发电压的多器件半导体器件的均匀触发的结构和电路技术
公开(公告)号：US20080237721A1
公开(公告)日：2008-10-02
申请号：US11692481
申请日：2007-03-28
申请人： Michel J. Abou-Khalil , Robert Gauthier , Hongmei Li , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert Gauthier , Hongmei Li , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L23/60
CPC分类号： H01L27/0277 , H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An external current injection source is provided to individual fingers of a multi-finger semiconductor device to provide the same trigger voltage across the multiple fingers. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source is adjusted so that each finger has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.
摘要翻译：外部电流注入源被提供给多指半导体器件的各个指状物，以跨多个指状物提供相同的触发电压。例如，外部注入电流被提供给MOSFET的主体或晶闸管的栅极。调整来自每个外部电流注入源的供给电流的大小，使得每个手指具有相同的触发电压。外部电流供应电路可以包括二极管或RC触发MOSFET。可以调谐外部电流供应电路的组件以实现多指半导体器件的所有指状物上期望的预定触发电压。

10. 发明申请

US20080193433A1 Novel non-toxic composition and use thereof for treatment a degenerative or an immune-related disease 审中-公开
标题翻译：新型无毒组合物及其用于治疗退行性或免疫相关疾病的用途
公开(公告)号：US20080193433A1
公开(公告)日：2008-08-14
申请号：US11987196
申请日：2007-11-28
申请人： Robert Gauthier , Lee H. Lorenzen
发明人： Robert Gauthier , Lee H. Lorenzen
IPC分类号： A61K38/47 , A61K38/43 , A61K38/48 , A61P35/00 , A61P31/18 , A61P37/00
CPC分类号： A61K36/00 , A61K33/00 , A61K38/018 , A61K45/06 , A61K2300/00
摘要： There is provided a non-toxic composition and method of using such for treating a degenerative or an immune-related disease. The non-toxic composition comprises a sprouted grain composition comprising digestive enzymes, a clustered water composition, and a substantially undenatured whey protein composition.
摘要翻译：提供了一种无毒的组合物和使用其来治疗退行性或免疫相关疾病的方法。无毒组合物包含发芽谷物组合物，其包含消化酶，聚集水组合物和基本上未变性的乳清蛋白组合物。

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