专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08456785B2 Semiconductor ESD device and method 有权
标题翻译：半导体ESD器件及方法
公开(公告)号：US08456785B2
公开(公告)日：2013-06-04
申请号：US12911582
申请日：2010-10-25
申请人： Krzysztof Domanski , Cornelius Christian Russ , David Alvarez , Wolfgang Soldner
发明人： Krzysztof Domanski , Cornelius Christian Russ , David Alvarez , Wolfgang Soldner
IPC分类号： H02H9/00 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier.
摘要翻译：实施例半导体器件具有设置在设置在半导体本体内的ESD器件区域内的第二器件区域上的第一器件区域。还包括设置在第二器件区域上的第三器件区域，与第二器件区域相邻的第四器件区域，设置在第四器件区域内的第五器件区域以及与第四器件区域相邻的第六器件区域。第一和第四区域具有第一半导体类型，并且第二，第三，第五和第六区域具有与第一导电类型相反的第二导电类型。第四器件区域和第六器件区域之间的界面形成二极管结。第一，第二，第四和第五器件区域形成可控硅整流器。

2. 发明申请

US20120176710A1 Semiconductor ESD Circuit and Method 有权
标题翻译：半导体ESD电路及方法
公开(公告)号：US20120176710A1
公开(公告)日：2012-07-12
申请号：US12987658
申请日：2011-01-10
申请人： Krzysztof Domanski , Wolfgang Soldner , Cornelius Christian Russ , David Alvarez , Adrien Ille
发明人： Krzysztof Domanski , Wolfgang Soldner , Cornelius Christian Russ , David Alvarez , Adrien Ille
IPC分类号： H02H9/00 , H01L29/78
CPC分类号： H02H9/046 , H01L27/0285 , H01L29/0692 , H01L29/1083
摘要： In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
摘要翻译：在一个实施例中，用于在第一节点和第二节点之间提供保护的静电放电（ESD）电路包括具有耦合到第一节点的第一源极/漏极和耦合到中间节点的第二源极/漏极的第一MOS器件。 ESD电路还包括耦合在第一MOS器件的栅极和第一节点之间的第一电容器，耦合在第一MOS器件的中间节点的栅极之间的第一电阻器，第二MOS / 中间节点和耦合到第二节点的第二源极/漏极，耦合在第二MOS器件的栅极和第一节点之间的第二电容器，以及耦合在第二MOS器件的栅极和第二节点之间的第二电阻器。

3. 发明申请

US20120099229A1 Semiconductor ESD Device and Method 有权
标题翻译：半导体ESD器件及方法
公开(公告)号：US20120099229A1
公开(公告)日：2012-04-26
申请号：US12911582
申请日：2010-10-25
申请人： Krzysztof Domanski , Cornelius Christian Russ , David Alvarez , Wolfgang Soldner
发明人： Krzysztof Domanski , Cornelius Christian Russ , David Alvarez , Wolfgang Soldner
IPC分类号： H02H9/04 , H01L29/73
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier.
摘要翻译：实施例半导体器件具有设置在设置在半导体本体内的ESD器件区域内的第二器件区域上的第一器件区域。还包括设置在第二器件区域上的第三器件区域，与第二器件区域相邻的第四器件区域，设置在第四器件区域内的第五器件区域以及与第四器件区域相邻的第六器件区域。第一和第四区域具有第一半导体类型，并且第二，第三，第五和第六区域具有与第一导电类型相反的第二导电类型。第四器件区域和第六器件区域之间的界面形成二极管结。第一，第二，第四和第五器件区域形成可控硅整流器。

4. 发明授权

US09013842B2 Semiconductor ESD circuit and method 有权
标题翻译：半导体ESD电路及方法
公开(公告)号：US09013842B2
公开(公告)日：2015-04-21
申请号：US12987658
申请日：2011-01-10
申请人： Krzysztof Domanski , Wolfgang Soldner , Cornelius Christian Russ , David Alvarez , Adrien Ille
发明人： Krzysztof Domanski , Wolfgang Soldner , Cornelius Christian Russ , David Alvarez , Adrien Ille
IPC分类号： H02H9/00 , H01L27/02 , H01L29/06 , H01L29/10 , H02H9/04
CPC分类号： H02H9/046 , H01L27/0285 , H01L29/0692 , H01L29/1083
摘要： In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.
摘要翻译：在一个实施例中，用于在第一节点和第二节点之间提供保护的静电放电（ESD）电路包括具有耦合到第一节点的第一源极/漏极和耦合到中间节点的第二源极/漏极的第一MOS器件。 ESD电路还包括耦合在第一MOS器件的栅极和第一节点之间的第一电容器，耦合在第一MOS器件的中间节点的栅极之间的第一电阻器，第二MOS / 中间节点和耦合到第二节点的第二源极/漏极，耦合在第二MOS器件的栅极和第一节点之间的第二电容器，以及耦合在第二MOS器件的栅极和第二节点之间的第二电阻器。

5. 发明申请

US20120154961A1 ELECTROSTATIC DISCHARGE BLOCKING CIRCUITS 有权
标题翻译：静电放电阻塞电路
公开(公告)号：US20120154961A1
公开(公告)日：2012-06-21
申请号：US12975069
申请日：2010-12-21
申请人： Christian Russ , Wolfgang Soldner , Gernot Langguth , David Alvarez , Krzysztof Domanski , Klaus von Arnim
发明人： Christian Russ , Wolfgang Soldner , Gernot Langguth , David Alvarez , Krzysztof Domanski , Klaus von Arnim
IPC分类号： H02H9/04
CPC分类号： H02H9/046 , H02H3/202 , H02H3/22
摘要： Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.
摘要翻译：描述对应于静电放电阻断电路的技术和架构。

6. 发明申请

US20120154962A1 ELECTROSTATIC DISCHARGE CLAMPING DEVICES WITH TRACING CIRCUITRY 有权
标题翻译：具有跟踪电路的静电放电钳位装置
公开(公告)号：US20120154962A1
公开(公告)日：2012-06-21
申请号：US12975210
申请日：2010-12-21
申请人： Christian Russ , Wolfgang Soldner , Klaus von Arnim , David Alvarez , Krzysztof Domanski , Gernot Langguth
发明人： Christian Russ , Wolfgang Soldner , Klaus von Arnim , David Alvarez , Krzysztof Domanski , Gernot Langguth
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L27/0285
摘要： Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.
摘要翻译：描述对应于具有跟踪电路的静电放电钳位电路的技术和架构。

7. 发明授权

US09197061B2 Electrostatic discharge clamping devices with tracing circuitry 有权
标题翻译：具有跟踪电路的静电放电钳位装置
公开(公告)号：US09197061B2
公开(公告)日：2015-11-24
申请号：US12975210
申请日：2010-12-21
申请人： Christian Russ , Wolfgang Soldner , Klaus von Arnim , David Alvarez , Krzysztof Domanski , Gernot Langguth
发明人： Christian Russ , Wolfgang Soldner , Klaus von Arnim , David Alvarez , Krzysztof Domanski , Gernot Langguth
IPC分类号： H02H9/00 , H02H9/04 , H01L27/02
CPC分类号： H02H9/046 , H01L27/0285
摘要： Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.
摘要翻译：描述对应于具有跟踪电路的静电放电钳位电路的技术和架构。

8. 发明授权

US08976496B2 Electrostatic discharge blocking circuits 有权
标题翻译：静电放电阻塞电路
公开(公告)号：US08976496B2
公开(公告)日：2015-03-10
申请号：US12975069
申请日：2010-12-21
申请人： Christian Russ , Wolfgang Soldner , Gernot Langguth , David Alvarez , Krzysztof Domanski , Klaus von Arnim
发明人： Christian Russ , Wolfgang Soldner , Gernot Langguth , David Alvarez , Krzysztof Domanski , Klaus von Arnim
IPC分类号： H02H9/04 , H02H3/22 , H02H3/20
CPC分类号： H02H9/046 , H02H3/202 , H02H3/22
摘要： Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.
摘要翻译：描述对应于静电放电阻断电路的技术和架构。

9. 发明授权

US08198651B2 Electro static discharge protection device 有权
标题翻译：静电放电保护装置
公开(公告)号：US08198651B2
公开(公告)日：2012-06-12
申请号：US12250436
申请日：2008-10-13
申请人： Gernot Langguth , Wolfgang Soldner , Cornelius Christian Russ
发明人： Gernot Langguth , Wolfgang Soldner , Cornelius Christian Russ
IPC分类号： H01L29/02
CPC分类号： H01L29/7436 , H01L27/0262 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type. A third heavily doped region is disposed in the second low doped region, the third heavily doped region comprising the second conductivity type and being coupled to a second power supply potential node.
摘要翻译：公开了一种用于防止静电放电的半导体器件。在一个实施例中，半导体器件包括设置在衬底中的第一低掺杂区域，设置在第一低掺杂区域内的第一重掺杂区域，第一重掺杂区域包括第一导电类型，第一低掺杂区域包括第二导电类型，第一和第二导电类型是相反的，第一重掺杂区域耦合到待保护的节点。所述半导体器件还包括耦合到第一电源电势节点的第二重掺杂区域，所述第二重掺杂区域由所述第一低掺杂区域的一部分与所述第一重掺杂区域分离，以及邻近设置的第二低掺杂区域第一低掺杂区域，第二低掺杂区域包括第一导电类型。第三重掺杂区域设置在第二低掺杂区域中，第三重掺杂区域包括第二导电类型并耦合到第二电源电位节点。

10. 发明申请

US20100090283A1 Electro Static Discharge Protection Device 有权
标题翻译：静电放电保护装置
公开(公告)号：US20100090283A1
公开(公告)日：2010-04-15
申请号：US12250436
申请日：2008-10-13
申请人： Gernot Langguth , Wolfgang Soldner , Cornelius Christian Russ
发明人： Gernot Langguth , Wolfgang Soldner , Cornelius Christian Russ
IPC分类号： H01L23/58 , H01L21/04
CPC分类号： H01L29/7436 , H01L27/0262 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type. A third heavily doped region is disposed in the second low doped region, the third heavily doped region comprising the second conductivity type and being coupled to a second power supply potential node.
摘要翻译：公开了一种用于防止静电放电的半导体器件。在一个实施例中，半导体器件包括设置在衬底中的第一低掺杂区域，设置在第一低掺杂区域内的第一重掺杂区域，第一重掺杂区域包括第一导电类型，第一低掺杂区域包括第二导电类型，第一和第二导电类型是相反的，第一重掺杂区域耦合到待保护的节点。所述半导体器件还包括耦合到第一电源电势节点的第二重掺杂区域，所述第二重掺杂区域由所述第一低掺杂区域的一部分与所述第一重掺杂区域分离，以及邻近设置的第二低掺杂区域第一低掺杂区域，第二低掺杂区域包括第一导电类型。第三重掺杂区域设置在第二低掺杂区域中，第三重掺杂区域包括第二导电类型并耦合到第二电源电位节点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式