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1. 发明授权

US06340897B1 Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory 有权
标题翻译：可编程逻辑阵列集成电路，具有可配置为随机存取或FIFO存储器的通用存储器
公开(公告)号：US06340897B1
公开(公告)日：2002-01-22
申请号：US09481781
申请日：2000-01-11
申请人： Craig S. Lytle , Donald F. Faria
发明人： Craig S. Lytle , Donald F. Faria
IPC分类号： H03K19177
CPC分类号： H03K19/17704 , H03K19/17 , H03K19/177 , H03K19/17736
摘要： A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).
摘要翻译：一种包含存储块的可编程逻辑器件集成电路。存储器块（250）是可配置为随机存取存储器（RAM）或先进先出（FIFO）存储器的通用存储器。在一个实施例中，存储块（250）的组织可以具有可变的字大小和深度大小。存储器块（250）耦合到可编程互连阵列（213）。来自可编程互连阵列（213）的信号可以可编程地耦合到存储器块的数据，地址和控制输入。来自存储器块的数据输出和状态标志信号可编程地耦合到可编程互连阵列（213）。

2. 发明授权

US06294928B1 Programmable logic device with highly routable interconnect 失效
标题翻译：具有高度可路由互连的可编程逻辑器件
公开(公告)号：US06294928B1
公开(公告)日：2001-09-25
申请号：US08838398
申请日：1997-04-03
申请人： Craig S. Lytle , Kerry S. Veenstra , Francis B. Heile
发明人： Craig S. Lytle , Kerry S. Veenstra , Francis B. Heile
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17728
摘要： A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (A-200) comprises an input multiplexer region (A-504), logic elements (A-300), input-output pins (A-516), and output multiplexer region (A-508). Furthermore, a logic device and a method of operating a logic device. The device includes logic elements (B-240) that perform desired logic functions and routing functions. The logic elements (B-240) are arranged in larger logic blocks known as logic array blocks (B-230) that have local interconnection systems. The logic array blocks (B-230) are configured to provide global interconnections. The configuration provides a Clos network, whereby a signal may be routed from any input to any output without blocking.
摘要翻译：具有高可路由可编程互连结构的可编程逻辑器件架构。逻辑阵列块（LAB），可编程互连结构和其他逻辑元件的布置形成了Clos网络。在满足特定约束之后，保证架构的路由。当中间阶段没有扇出的时候，这个架构是可行的。 AAB（A-200）包括输入多路复用器区域（A-504），逻辑元件（A-300），输入输出引脚（A-516）和输出多路复用器区域（A-508）。此外，逻辑设备和操作逻辑设备的方法。该设备包括执行所需逻辑功能和路由功能的逻辑元件（B-240）。逻辑元件（B-240）被布置在具有本地互连系统的被称为逻辑阵列块（B-230）的较大逻辑块中。逻辑阵列块（B-230）被配置为提供全局互连。该配置提供了一个Clos网络，从而信号可以从任何输入路由到任何输出而不阻塞。

3. 发明授权

US6134166A Programmable logic array integrated circuit incorporating a first-in first-out memory 失效
标题翻译：包含先进先出存储器的可编程逻辑阵列集成电路
公开(公告)号：US6134166A
公开(公告)日：2000-10-17
申请号：US19423
申请日：1998-02-05
申请人： Craig S. Lytle , Donald F. Faria
发明人： Craig S. Lytle , Donald F. Faria
IPC分类号： G06F5/10 , G11C19/00 , H03K19/177 , G11C7/00
CPC分类号： H03K19/17704 , G11C19/00 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/1778 , G06F5/10
摘要： A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.
摘要翻译：一种结合先进先出存储块（250）的可编程逻辑器件集成电路。先进先出的存储块（250）耦合到可编程互连阵列（213）。来自逻辑阵列块（LAB）（201）的信号被连接到先进先出存储器（250）的控制输入。在一个实施例中，可编程互连阵列（213）可以可编程地耦合到先进先出存储器块的控制输入（259）。来自先进先出存储块（250）的状态标志信号（276）可编程地耦合到可编程互连阵列（213）。数据输入（263）和数据输出（261）到先进先出存储器块（250）可以耦合到外部片外电路。

4. 发明授权

US5166604A Methods and apparatus for facilitating scan testing of asynchronous logic circuitry 失效
标题翻译：用于促进异步逻辑电路的扫描测试的方法和装置
公开(公告)号：US5166604A
公开(公告)日：1992-11-24
申请号：US611974
申请日：1990-11-13
申请人： Bahram Ahanin , Craig S. Lytle , Ricky W. Ho
发明人： Bahram Ahanin , Craig S. Lytle , Ricky W. Ho
IPC分类号： G01R31/317 , G01R31/3185
CPC分类号： G01R31/318558 , G01R31/31707
摘要： Scan testing of asynchronous logic circuitry is facilitated by gating off the asynchronous inputs to flip-flops during scan testing. If desired, the asynchronous inputs which are gated off in this manner may themselves terminals or scan registers during testing. Alternatively, the asynchronous inputs which are gated could be tested by selectively enabling the signals at strategic points during scan testing. The number of input terminals required to control the test mode may be reduced by providing registers for storing test control signals applied to normal input terminals at the beginning of a test cycle. Once these test control signals are stored, the normal input terminals are free to return to their normal use.
摘要翻译：通过在扫描测试期间门控异步输入到触发器来促进异步逻辑电路的扫描测试。如果需要，以这种方式门控的异步输入端可能在测试期间本身可以是终端或扫描寄存器。或者，可以通过在扫描测试期间在战略点上选择性地启用信号来测试门控的异步输入。通过提供用于存储在测试周期开始时施加到正常输入端的测试控制信号的寄存器，可以减少控制测试模式所需的输入端子的数量。一旦存储了这些测试控制信号，正常输入端可以自由返回正常使用。

5. 发明授权

US5570040A Programmable logic array integrated circuit incorporating a first-in first-out memory 失效
公开(公告)号：US5570040A
公开(公告)日：1996-10-29
申请号：US408504
申请日：1995-03-22
申请人： Craig S. Lytle , Donald F. Faria
发明人： Craig S. Lytle , Donald F. Faria
IPC分类号： G11C19/00 , H03K19/177
CPC分类号： H03K19/17736 , G11C19/00 , H03K19/17704
摘要： A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.

6. 发明授权

US5376844A Programmable logic device with multiplexer-based programmable interconnections 失效
标题翻译：可编程逻辑器件，具有基于复用器的可编程互连
公开(公告)号：US5376844A
公开(公告)日：1994-12-27
申请号：US39944
申请日：1993-03-29
申请人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
发明人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
摘要翻译：可编程逻辑阵列集成电路具有被分组成多个相互排斥的组的多个可编程逻辑元件。每个组包括与该组唯一相关联的信号导体，用于在该组中的可编程逻辑元件之间传送信号。提供其他信号导体用于在组之间传送信号。多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

7. 发明授权

US5285153A Apparatus for facilitating scan testing of asynchronous logic circuitry 失效
标题翻译：用于促进异步逻辑电路的扫描测试的装置
公开(公告)号：US5285153A
公开(公告)日：1994-02-08
申请号：US947729
申请日：1992-09-21
申请人： Bahram Ahanin , Craig S. Lytle , Ricky W. Ho
发明人： Bahram Ahanin , Craig S. Lytle , Ricky W. Ho
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318558 , G01R31/31707
摘要： Scan testing of asynchronous logic circuitry is facilitated by gating off the asynchronous inputs to flip-flops during scan testing. If desired, the asynchronous inputs which are gated off in this manner may themselves be tested by connecting them to one or more output terminals or scan registers during testing. Alternatively, the asynchronous inputs which are gated could be tested by selectively enabling the signals at strategic points during scan testing. The number of input terminals required to control the test mode may be reduced by providing registers for storing test control signals applied to normal input terminals at the beginning of a test cycle. Once these test control signals are stored, the normal input terminals are free to return to their normal use.
摘要翻译：通过在扫描测试期间门控异步输入到触发器来促进异步逻辑电路的扫描测试。如果需要，以这种方式门控的异步输入本身可以通过在测试期间将它们连接到一个或多个输出端子或扫描寄存器来进行测试。或者，可以通过在扫描测试期间在战略点上选择性地启用信号来测试门控的异步输入。通过提供用于存储在测试周期开始时施加到正常输入端的测试控制信号的寄存器，可以减少控制测试模式所需的输入端子的数量。一旦存储了这些测试控制信号，正常输入端可以自由返回正常使用。

8. 发明授权

US6049223A Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory 失效
公开(公告)号：US6049223A
公开(公告)日：2000-04-11
申请号：US707705
申请日：1996-07-24
申请人： Craig S. Lytle , Donald F. Faria
发明人： Craig S. Lytle , Donald F. Faria
IPC分类号： H03K19/17 , H03K19/177
CPC分类号： H03K19/17704 , H03K19/177 , H03K19/17736 , H03K19/17
摘要： A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).

9. 发明授权

US5260611A Programmable logic array having local and long distance conductors 失效
标题翻译：具有本地和长距离导体的可编程逻辑阵列
公开(公告)号：US5260611A
公开(公告)日：1993-11-09
申请号：US880942
申请日：1992-05-08
申请人： Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Bruce B. Pedersen , Kerry Veenstra
发明人： Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Bruce B. Pedersen , Kerry Veenstra
IPC分类号： H01L21/82 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728 , H03K19/1774 , H03K19/17792
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.
摘要翻译：可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的网络。提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。

10. 发明授权

US5260610A Programmable logic element interconnections for programmable logic array integrated circuits 失效
标题翻译：可编程逻辑阵列集成电路的可编程逻辑元件互连
公开(公告)号：US5260610A
公开(公告)日：1993-11-09
申请号：US754017
申请日：1991-09-03
申请人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
发明人： Bruce B. Pedersen , Richard G. Cliff , Bahram Ahanin , Craig S. Lytle , Francis B. Heile , Kerry S. Veenstra
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

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