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1. 发明授权

US07366822B2 Semiconductor memory device capable of reading and writing data at the same time 有权
标题翻译：能够同时读取和写入数据的半导体存储器件
公开(公告)号：US07366822B2
公开(公告)日：2008-04-29
申请号：US10840268
申请日：2004-05-07
申请人： Jin-Seok Kwak , Young-Hyun Jun , Seong-Jin Jang , Sang-Bo Lee , Min-Sang Park , Chul-Soo Kim
发明人： Jin-Seok Kwak , Young-Hyun Jun , Seong-Jin Jang , Sang-Bo Lee , Min-Sang Park , Chul-Soo Kim
IPC分类号： G06F12/00 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/1072 , G11C11/4082 , G11C11/4087
摘要： A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.
摘要翻译：半导体存储器件包括多个存储体。数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少。

2. 发明授权

US07092299B2 Memory devices, systems and methods using selective on-die termination 有权
标题翻译：存储器件，系统和使用选择性片上端接的方法
公开(公告)号：US07092299B2
公开(公告)日：2006-08-15
申请号：US10792623
申请日：2004-03-03
申请人： Jin-Seok Kwak , Seong-Jin Jang , Young-Hyun Jun
发明人： Jin-Seok Kwak , Seong-Jin Jang , Young-Hyun Jun
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/10 , G11C7/1048
摘要： A memory system includes first and second memory devices having commonly connected data terminals and commonly connected memory control signal terminals, e.g., devices in respective first and second independently selectable memory banks that share common data lines and common memory control signal lines, such as column address strobe, row address strobe, write enable, and address signal lines. The first and second memory devices includes respective selective on-die termination (ODT) circuits configured to selectively provide first and second termination impedances at their respective data terminals responsive to a memory control signal at the commonly connected memory control signal terminals. The selective ODT circuits may produce the first termination impedance responsive to a memory write operation, and may produce the second termination impedance responsive to a memory read operation and/or expiration of a predetermined time interval following termination of the memory write operation. Preferably, the first termination impedance is less than the second termination impedance, and the selective ODT circuits provide the first termination impedance responsive to the memory write operation irrespective of which of the first and second memory devices is being written to.
摘要翻译：存储器系统包括具有共同连接的数据端子和共同连接的存储器控制信号端子的第一和第二存储器件，例如共享公共数据线和公共存储器控制信号线的各自的第一和第二可独立选择的存储体中的器件，诸如列地址选通，行地址选通，写使能和地址信号线。第一和第二存储器件包括相应的选择性管芯端接（ODT）电路，其被配置为响应于在共同连接的存储器控制信号端子处的存储器控制信号在它们各自的数据端口选择性地提供第一和第二终端阻抗。响应于存储器写入操作，选择性ODT电路可以产生第一终止阻抗，并且可以在存储器写入操作终止之后响应于存储器读取操作和/或预定时间间隔的期满而产生第二终止阻抗。优选地，第一终端阻抗小于第二终端阻抗，并且选择性ODT电路响应于存储器写入操作提供第一终止阻抗，而与正在写入的第一和第二存储器件中的哪一个无关。

3. 发明申请

US20110205822A1 BITLINE SENSE AMPLIFIER, MEMORY CORE INCLUDING THE SAME AND METHOD OF SENSING CHARGE FROM A MEMORY CELL 有权
标题翻译：位线感测放大器，包含其的存储器核心和从存储器单元感测电荷的方法
公开(公告)号：US20110205822A1
公开(公告)日：2011-08-25
申请号：US13006832
申请日：2011-01-14
申请人： Joung-Yeal Kim , Seong-Jin Jang , Jin-Seok Kwak
发明人： Joung-Yeal Kim , Seong-Jin Jang , Jin-Seok Kwak
IPC分类号： G11C7/06 , G01R19/00
CPC分类号： G11C7/12 , G11C7/065 , G11C11/4091 , G11C11/4094
摘要： A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.
摘要翻译：位线读出放大器包括预感测单元和放大单元。预感测单元连接到第一位线和第二位线，并且被配置为通过基于至少一个预感测电压和电压电平的变化来控制第二位线的电压电平来执行预感测操作的第一个位线。放大单元被配置为通过基于第一电压信号和第二电压信号放大预感测电压差来执行主放大操作。预感测电压差表示在预感测操作之后第一位线的电压电平和第二位线的电压电平之间的差。

4. 发明授权

US06631090B1 Circuit and method for data output in synchronous semiconductor device 失效
标题翻译：同步半导体器件数据输出电路及方法
公开(公告)号：US06631090B1
公开(公告)日：2003-10-07
申请号：US10266789
申请日：2002-10-08
申请人： Jin-Seok Kwak , Seong-Jin Jang
发明人： Jin-Seok Kwak , Seong-Jin Jang
IPC分类号： G11C1604
CPC分类号： G11C7/106 , G11C7/1018 , G11C7/1051 , G11C2207/002
摘要： A data output circuit and method in a synchronous semiconductor device are described. The semiconductor device is preferably a wave pipelined synchronous semiconductor device. A first-stage or former-stage latch unit receives a first bit of a group of data bits to be output. A second-stage or latter-stage latch unit receives a second bit of the group of data bits. A buffering unit is interposed between the first and second stage latch units. The buffering unit receives the second bit from the second-stage latch unit and forwards the second bit to the first-stage latch unit.
摘要翻译：描述同步半导体器件中的数据输出电路和方法。半导体器件优选地是波长流水线同步半导体器件。第一级或前级锁存单元接收要输出的一组数据位的第一位。第二级或后级锁存单元接收该组数据位的第二位。缓冲单元插入在第一和第二级闩锁单元之间。缓冲单元从第二级锁存单元接收第二位，并将第二位转发到第一级锁存单元。

5. 发明申请

US20110044121A1 SEMICONDUCTOR MEMORY DEVICE HAVING DEVICE FOR CONTROLLING BIT LINE LOADING AND IMPROVING SENSING EFFICIENCY OF BIT LINE SENSE AMPLIFIER 审中-公开
标题翻译：具有用于控制位线负载的设备的半导体存储器件和提高位线感测放大器的感测效率
公开(公告)号：US20110044121A1
公开(公告)日：2011-02-24
申请号：US12860484
申请日：2010-08-20
申请人： Joung-Yeal Kim , Soo-Bong Chang , Seong-Jin Jang , Jin-Seok Kwak , Dong-Hak Shin
发明人： Joung-Yeal Kim , Soo-Bong Chang , Seong-Jin Jang , Jin-Seok Kwak , Dong-Hak Shin
IPC分类号： G11C7/06
CPC分类号： G11C11/4094 , G11C11/4091 , G11C2207/005
摘要： A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal.
摘要翻译：半导体存储器件包括存储单元阵列块，该存储单元阵列块包括多个存储单元，每个存储单元分别连接到多个位线中的一个位线和多个字线中的一个，连接到多个位线的一半的读出放大器，读出放大器，用于感测和放大位线的每一个之间的电压和相应的互补位线; 以及连接到存储单元阵列块的多个位线的一半的虚拟块，用于根据虚拟负载信号控制存储单元阵列块上的负载与虚拟块上的负载不同的虚拟块。

6. 发明授权

US07200069B2 Semiconductor memory device having external data load signal synchronous with data strobe signal and serial-to-parallel data prefetch method thereof 失效
标题翻译：具有与数据选通信号同步的外部数据负载信号及其串并行数据预取方法的半导体存储器件
公开(公告)号：US07200069B2
公开(公告)日：2007-04-03
申请号：US10273512
申请日：2002-10-18
申请人： Seong-Jin Jang , Jin-Seok Kwak
发明人： Seong-Jin Jang , Jin-Seok Kwak
IPC分类号： G06F12/00
CPC分类号： G11C7/1087 , G06F13/1689 , G11C7/1078 , G11C2207/107
摘要： A semiconductor memory system, a memory control circuit and a semiconductor memory device are disclosed. The system includes a memory control circuit for generating a data strobe signal and a data load signal in synchronization with each other. The memory circuit, which can be an SDRAM memory circuit, receives the data strobe signal and the data load signal and writes data in response to the two synchronous signals. Because the signal are synchronous, parameters introduced by timing variations caused by different signal domains are eliminated. As a result, high-frequency operation of the system is greatly improved.
摘要翻译：公开了半导体存储器系统，存储器控制电路和半导体存储器件。该系统包括用于彼此同步地产生数据选通信号和数据负载信号的存储器控制电路。可以是SDRAM存储器电路的存储电路接收数据选通信号和数据负载信号，并响应于两个同步信号写入数据。由于信号是同步的，消除了由不同信号域引起的定时变化引入的参数。结果，系统的高频操作大大提高。

7. 发明授权

US06762620B2 Circuit and method for controlling on-die signal termination 有权
标题翻译：用于控制片上信号终止的电路和方法
公开(公告)号：US06762620B2
公开(公告)日：2004-07-13
申请号：US10235694
申请日：2002-09-05
申请人： Seong-Jin Jang , Jin-Seok Kwak
发明人： Seong-Jin Jang , Jin-Seok Kwak
IPC分类号： H03K1716
CPC分类号： H04L25/0298 , H03K19/0005
摘要： A system and method allows for multiple modes of termination, including termination by a fixed value that is preprogrammed, and by a variable value that can, for example, be measured and determined by a self-calibration circuit. Multiple termination values can be achieved within a single device. This configuration is especially applicable to devices that have different loadings for address and data signals, for example in a configuration having a common, shared address bus, and multiple, localized data buses.
摘要翻译：系统和方法允许多种终止模式，包括通过预编程的固定值的终止，以及可以例如由自校准电路测量和确定的可变值。可以在单个设备内实现多个终止值。该配置特别适用于具有地址和数据信号的不同负载的设备，例如在具有公共共享地址总线和多个本地化数据总线的配置中。

8. 发明授权

US08432762B2 Bitline sense amplifier, memory core including the same and method of sensing charge from a memory cell 有权
标题翻译：位线读出放大器，包括相同的存储器核心以及从存储器单元感测电荷的方法
公开(公告)号：US08432762B2
公开(公告)日：2013-04-30
申请号：US13006832
申请日：2011-01-14
申请人： Joung-Yeal Kim , Seong-Jin Jang , Jin-Seok Kwak
发明人： Joung-Yeal Kim , Seong-Jin Jang , Jin-Seok Kwak
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/065 , G11C11/4091 , G11C11/4094
摘要： A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.
摘要翻译：位线读出放大器包括预感测单元和放大单元。预感测单元连接到第一位线和第二位线，并且被配置为通过基于至少一个预感测电压和电压电平的变化来控制第二位线的电压电平来执行预感测操作的第一个位线。放大单元被配置为通过基于第一电压信号和第二电压信号放大预感测电压差来执行主放大操作。预感测电压差表示在预感测操作之后第一位线的电压电平和第二位线的电压电平之间的差。

9. 发明申请

US20050068840A1 Methods of selectively activating word line segments enabled by row addresses and semiconductor memory devices having partial activation commands of word line 失效
标题翻译：选择性地激活由行地址启用的字线段和具有字线的部分激活命令的半导体存储器件的方法
公开(公告)号：US20050068840A1
公开(公告)日：2005-03-31
申请号：US10943514
申请日：2004-09-17
申请人： Min-Sang Park , Yu-Lim Lee , Seong-Jin Jang
发明人： Min-Sang Park , Yu-Lim Lee , Seong-Jin Jang
IPC分类号： G11C11/407 , G11C8/02 , G11C8/08 , G11C11/401 , G11C11/4063
CPC分类号： G11C8/12
摘要： A method for activating a word line segment of a semiconductor memory selected based on a row address provided to the memory can include activating a first word line segment selected by a row address and a command type and avoiding activating a second word line segment selected by the row address. Related devices are also disclosed.
摘要翻译：用于激活基于提供给存储器的行地址选择的半导体存储器的字线段的方法可以包括激活由行地址和命令类型选择的第一字线段，并且避免激活由第二字线段选择的第二字线段行地址。还公开了相关设备。

10. 发明授权

US07187615B2 Methods of selectively activating word line segments enabled by row addresses and semiconductor memory devices having partial activation commands of word line 失效
标题翻译：选择性地激活由行地址启用的字线段和具有字线的部分激活命令的半导体存储器件的方法
公开(公告)号：US07187615B2
公开(公告)日：2007-03-06
申请号：US10943514
申请日：2004-09-17
申请人： Min-Sang Park , Yu-Lim Lee , Seong-Jin Jang
发明人： Min-Sang Park , Yu-Lim Lee , Seong-Jin Jang
IPC分类号： G11C8/00
CPC分类号： G11C8/12
摘要： A method for activating a word line segment of a semiconductor memory selected based on a row address provided to the memory can include activating a first word line segment selected by a row address and a command type and avoiding activating a second word line segment selected by the row address. Related devices are also disclosed.
摘要翻译：用于激活基于提供给存储器的行地址选择的半导体存储器的字线段的方法可以包括激活由行地址和命令类型选择的第一字线段，并且避免激活由第二字线段选择的第二字线段行地址。还公开了相关设备。

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