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    • 2. 发明申请
      US20060224814A1 Semiconductor memory devices having controllable input/output bit architectures and related methods 有权
    • Semiconductor memory devices having controllable input/output bit architectures and related methods
    • 具有可控输入/输出位结构和相关方法的半导体存储器件
    • US20060224814A1
    • 2006-10-05
    • US11358798
    • 2006-02-21
    • Sung-Hoon Kim , Seong-Jin Jang , Su-Jin Park
    • Sung-Hoon Kim , Seong-Jin Jang , Su-Jin Park
    • G06F12/06
    • G11C7/22
    • A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through Nth data bits and/or to provide first through Nth data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal. The second unit memory device may be configured to receive (N+1)th through 2Nth data bits and/or to provide (N+1)th through 2Nth data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal. Related methods are also discussed.
    • 半导体存储器件可以包括半导体衬底，衬底上的第一单元存储器件和衬底上的第二单元存储器件。 第一单元存储器件可以被配置为响应于命令接收第一至第N个/或以上数据位和/或向外部设备提供第一至第N个/ 信号，地址信号和时钟信号，以及响应于第一芯片选择信号。 第二单元存储器件可以被配置为通过2N个第（N）个数据位接收（N + 1）个第个和/或提供（N + 1） 响应于命令信号，地址信号和时钟信号，以及响应于第二芯片选择信号，向外部设备提供/ SUP>至2N第数据位。 还讨论了相关方法。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US06451637B1 Method of forming a polycrystalline silicon film 有权
    • Method of forming a polycrystalline silicon film
    • 形成多晶硅膜的方法
    • US06451637B1
    • 2002-09-17
    • US09493201
    • 2000-01-28
    • Jin Jang , Sung-Hoon Kim
    • Jin Jang , Sung-Hoon Kim
    • H01L2100
    • C30B1/023 , C30B29/06
    • The present invention related to a method of forming a polycrystalline silicon film which forms a polysilicon film by crystallizing silicon by means of carrying out plasma exposure and applying an electric field thereon. The present invention includes the steps of forming a metal plasma exposure layer on a substrate wherein the metal plasma exposure layer works as a catalyst for metal induced crystallization, and depositing amorphous silicon on the substrate on which the plasma exposure layer is formed while an electric field is applied thereon. The present invention enables to crystallize the whole film in such a short annealing time less than 10 minutes by forming a metal layer under a silicon layer by plasma particle exposure and, successively, by crystallizing silicon which is being formed under 520° C. And, the present invention reduces metal contamination in the crystallized silicon film as the amount of metal is easy to be controlled by plasma exposure time. Moreover, the present invention enables to form a polysilicon film several &mgr;m thick as it is easy to form polysilicon of which thickness does not matter.
    • 本发明涉及通过进行等离子体曝光和在其上施加电场而使硅结晶而形成多晶硅膜的多晶硅膜的形成方法。 本发明包括在基板上形成金属等离子体曝光层的步骤，其中金属等离子体曝光层用作金属诱导结晶的催化剂，并在其上形成等离子体曝光层的基板上沉积非晶硅，同时电场 施加在其上。 本发明能够通过在等离子体颗粒曝光下在硅层下形成金属层，并且通过在520℃下形成硅来结晶在短的退火时间，使其在短于10分钟的短时间内使整个膜结晶。 本发明通过等离子体曝光时间容易地控制金属的量来减少结晶硅膜中的金属污染。 此外，本发明能够形成几个厚度的多晶硅膜，因为容易形成厚度无关的多晶硅。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US07391634B2 Semiconductor memory devices having controllable input/output bit architectures 有权
    • Semiconductor memory devices having controllable input/output bit architectures
    • 具有可控输入/输出位体系结构的半导体存储器件
    • US07391634B2
    • 2008-06-24
    • US11358798
    • 2006-02-21
    • Sung-Hoon Kim , Seong-Jin Jang , Su-Jin Park
    • Sung-Hoon Kim , Seong-Jin Jang , Su-Jin Park
    • G11C5/02 , G11C5/06
    • G11C7/22
    • A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through Nth data bits and/or to provide first through Nth data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal. The second unit memory device may be configured to receive (N+1)th through 2Nth data bits and/or to provide (N+1)th through 2Nth data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal. Related methods are also discussed.
    • 半导体存储器件可以包括半导体衬底，衬底上的第一单元存储器件和衬底上的第二单元存储器件。 第一单元存储器件可以被配置为响应于命令接收第一至第N个/或以上数据位和/或向外部设备提供第一至第N个/ 信号，地址信号和时钟信号，以及响应于第一芯片选择信号。 第二单元存储器件可以被配置为通过2N个第（N）个数据位接收（N + 1）个第个和/或提供（N + 1） 响应于命令信号，地址信号和时钟信号，以及响应于第二芯片选择信号，向外部设备提供/ SUP>至2N第数据位。 还讨论了相关方法。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US07580319B2 Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof 有权
    • Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof
    • 输入延迟控制电路，包括输入等待时间控制电路的半导体存储器件及其方法
    • US07580319B2
    • 2009-08-25
    • US11715478
    • 2007-03-08
    • Kyoung-Ho Kim , Seong-Jin Jang , Joung-Yeal Kim , Sung-Hoon Kim
    • Kyoung-Ho Kim , Seong-Jin Jang , Joung-Yeal Kim , Sung-Hoon Kim
    • G11C8/00
    • G11C7/1039 , G11C7/1045 , G11C7/1066 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4087 , G11C11/4096
    • An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an external clock signal, a command decoder configured to decode an external command signal to generate a write command signal and an input latency control circuit configured to gate an address signal in a pipeline mode to generate a column address signal and a bank address signal based on the internal clock signal, the write command signal and the write latency signal. The example input latency control circuit may include a master circuit configured to generate a column control signal and a first write address control signal based on an internal clock signal, a write command signal and a write latency signal, at least one column slave circuit configured to gate a first address signal in a pipeline mode to generate a column address signal in response to the column control signal and one of the first write address control signal and a second write address control signal and at least one bank slave circuit configured to gate a second address signal in the pipeline mode to generate the bank address signal in response to the column control signal and at least one of the first and second write address control signals.
    • 提供输入延迟控制电路，包括输入等待时间控制电路的半导体存储器件及其方法。 示例性半导体存储器件可以包括被配置为基于外部时钟信号产生内部时钟信号的时钟缓冲器，被配置为对外部命令信号进行解码以产生写入命令信号的命令解码器和被配置为对 地址信号，以及基于内部时钟信号，写入命令信号和写入等待时间信号产生列地址信号和存储体地址信号。 示例性输入延迟控制电路可以包括主电路，其被配置为基于内部时钟信号，写命令信号和写等待时间信号来生成列控制信号和第一写地址控制信号，至少一列从属电路被配置为 在流水线模式下门控第一地址信号，以响应于列控制信号和第一写地址控制信号和第二写地址控制信号中的一个产生列地址信号，并且至少一个存储体从属电路被配置为选通第二地址信号 地址信号，以响应于列控制信号和第一和第二写地址控制信号中的至少一个来产生存储体地址信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明申请
      US20070211556A1 Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof 有权
    • Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof
    • 输入延迟控制电路，包括输入等待时间控制电路的半导体存储器件及其方法
    • US20070211556A1
    • 2007-09-13
    • US11715478
    • 2007-03-08
    • Kyoung-Ho Kim , Seong-Jin Jang , Joung-Yeal Kim , Sung-Hoon Kim
    • Kyoung-Ho Kim , Seong-Jin Jang , Joung-Yeal Kim , Sung-Hoon Kim
    • G11C8/00 , G11C7/00
    • G11C7/1039 , G11C7/1045 , G11C7/1066 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4087 , G11C11/4096
    • An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an external clock signal, a command decoder configured to decode an external command signal to generate a write command signal and an input latency control circuit configured to gate an address signal in a pipeline mode to generate a column address signal and a bank address signal based on the internal clock signal, the write command signal and the write latency signal. The example input latency control circuit may include a master circuit configured to generate a column control signal and a first write address control signal based on an internal clock signal, a write command signal and a write latency signal, at least one column slave circuit configured to gate a first address signal in a pipeline mode to generate a column address signal in response to the column control signal and one of the first write address control signal and a second write address control signal and at least one bank slave circuit configured to gate a second address signal in the pipeline mode to generate the bank address signal in response to the column control signal and at least one of the first and second write address control signals.
    • 提供输入延迟控制电路，包括输入等待时间控制电路的半导体存储器件及其方法。 示例性半导体存储器件可以包括被配置为基于外部时钟信号产生内部时钟信号的时钟缓冲器，被配置为对外部命令信号进行解码以产生写入命令信号的命令解码器和被配置为对 地址信号，以及基于内部时钟信号，写入命令信号和写入等待时间信号产生列地址信号和存储体地址信号。 示例性输入延迟控制电路可以包括主电路，其被配置为基于内部时钟信号，写命令信号和写等待时间信号来生成列控制信号和第一写地址控制信号，至少一列从属电路被配置为 在流水线模式下门控第一地址信号，以响应于列控制信号和第一写地址控制信号和第二写地址控制信号中的一个产生列地址信号，并且至少一个存储体从属电路被配置为选通第二地址信号 地址信号，以响应于列控制信号和第一和第二写地址控制信号中的至少一个来产生存储体地址信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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