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1. 发明申请

US20130175661A1 Integrated Circuit Having Back Gating, Improved Isolation And Reduced Well Resistance And Method To Fabricate Same 审中-公开
标题翻译：集成电路具有后门控，改进隔离和降低电阻以及制造方法
公开(公告)号：US20130175661A1
公开(公告)日：2013-07-11
申请号：US13623198
申请日：2012-09-20
申请人： Jin Cai , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Jin Cai , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/76232 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A structure includes a silicon substrate; at least two wells in the silicon substrate; and a deep trench isolation (DTI) separating the two wells. The DTI has a top portion and a bottom portion having a width that is larger than a width of the top portion. The structure further includes at least two semiconductor devices disposed over one of the wells, where the at least two semiconductor devices are separated by a shallow trench isolation (STI). In the structure sidewalls of the top portion of the DTI and sidewalls of the STI are comprised of doped, re-crystallized silicon. The doped, re-crystallized silicon can be formed by an angled ion implant that uses, for example, one of Xe, In, BF2, B18H22, C16H10, Si, Ge or As as an implant species to amorphize the silicon, and by annealing the amorphized silicon to re-crystallize the amorphized silicon.
摘要翻译：一种结构包括硅衬底; 硅衬底中的至少两个孔; 和分离两口井的深沟槽隔离（DTI）。 DTI具有顶部和底部，其宽度大于顶部的宽度。该结构还包括设置在一个阱中的至少两个半导体器件，其中至少两个半导体器件由浅沟槽隔离（STI）隔开。在DTI的顶部部分和STI的侧壁的结构中，由掺杂的再结晶硅组成。掺杂的再结晶硅可以通过使用例如Xe，In，BF 2，B 18 H 22，C 16 H 10，Si，Ge或As中的一种的成角度的离子注入来形成，以使硅非晶化，并且通过退火非晶化硅使非晶化硅再结晶。

2. 发明授权

US08445356B1 Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same 有权
标题翻译：集成电路具有后门控，改进的隔离和降低的阱电阻以及制造相同的方法
公开(公告)号：US08445356B1
公开(公告)日：2013-05-21
申请号：US13343819
申请日：2012-01-05
申请人： Jin Cai , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Jin Cai , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/76
CPC分类号： H01L29/0649 , H01L21/76232 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： Disclosed is a method of forming a structure and a resulting structure. The method includes providing a semiconductor substrate; forming a first opening to a first depth in the semiconductor substrate; amorphizing semiconductor sidewalls of an upper portion of the first opening leaving unamorphized semiconductor sidewalls in a lower portion of the first opening; enlarging only the lower portion of the first opening using an etch process that is selective to the unamorphized semiconductor sidewalls; filling the first opening with an insulator material to form a deep trench isolation (DTI) structure and implanting a first well region and a second well region into the semiconductor substrate. The first well and the second well are separated from one another by the enlarged lower portion of the first opening. In the structure sidewalls of a top portion of a DTI and sidewalls of an STI are formed of doped, re-crystallized silicon.
摘要翻译：公开了一种形成结构和所得结构的方法。该方法包括：提供半导体衬底; 在所述半导体衬底中形成第一深度的第一开口; 将第一开口的上部的半导体侧壁非晶化，在第一开口的下部离开未变形的半导体侧壁; 使用对未变形的半导体侧壁具有选择性的蚀刻工艺仅扩大第一开口的下部; 用绝缘体材料填充第一开口以形成深沟槽隔离（DTI）结构，并将第一阱区域和第二阱区域注入到半导体衬底中。第一孔和第二孔通过第一开口的扩大的下部彼此分开。在DTI的顶部部分和STI侧壁中的结构中，由掺杂的再结晶硅形成。

3. 发明授权

US09059321B2 Buried channel field-effect transistors 有权
标题翻译：埋地通道场效应晶体管
公开(公告)号：US09059321B2
公开(公告)日：2015-06-16
申请号：US13470620
申请日：2012-05-14
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L21/338 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/10 , H01L29/786 , H01L29/78 , H01L21/8238 , H01L29/51
CPC分类号： H01L29/0642 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0692 , H01L29/1054 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78 , H01L29/78687 , H01L29/78696
摘要： Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric.
摘要翻译：用于形成掩埋沟道场效应晶体管的方法包括在具有第一类型的掺杂剂的衬底上掺杂源区和漏区; 在具有与第一类型相反的第二掺杂类型的沟道区域中的衬底上形成掺杂的屏蔽层，以使导电沟道偏离栅极 - 界面区域; 在所述掺杂屏蔽层上形成栅极电介质; 并在栅极电介质上形成栅极。

4. 发明授权

US09048108B2 Integrated circuit with on chip planar diode and CMOS devices 有权
标题翻译：集成电路与片上平面二极管和CMOS器件
公开(公告)号：US09048108B2
公开(公告)日：2015-06-02
申请号：US13478080
申请日：2012-05-22
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/8238 , H01L27/06
CPC分类号： H01L27/0629 , H01L29/0847 , H01L29/8611 , H01L29/868
摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.
摘要翻译：在同一芯片上形成二极管和一个或多个CMOS器件的电路，平面二极管和方法。该方法包括将二极管区域中的衬底的一部分与其它衬底区域电隔离。该方法还包括使二极管区域中的衬底凹陷。该方法还包括在二极管区域中外延形成在衬底上方的第一掺杂层，并在二极管区域中外延地形成第一掺杂层上方的第二掺杂层。

5. 发明授权

US09041116B2 Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs) 有权
公开(公告)号：US09041116B2
公开(公告)日：2015-05-26
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/092 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

6. 发明授权

US08928096B2 Buried-channel field-effect transistors 有权
标题翻译：掩埋通道场效应晶体管
公开(公告)号：US08928096B2
公开(公告)日：2015-01-06
申请号：US13474949
申请日：2012-05-18
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L21/02
CPC分类号： H01L29/0642 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0692 , H01L29/1054 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78 , H01L29/78687 , H01L29/78696
摘要： A buried-channel field-effect transistor includes a semiconductor layer formed on a substrate. The semiconductor layer includes doped source and drain regions and an undoped channel region. the transistor further includes a gate dielectric formed over the channel region and partially overlapping the source and drain regions; a gate formed over the gate dielectric; and a doped shielding layer between the gate dielectric and the semiconductor layer.
摘要翻译：掩埋沟道场效应晶体管包括形成在基板上的半导体层。半导体层包括掺杂的源极和漏极区域以及未掺杂的沟道区域。所述晶体管还包括形成在所述沟道区上并部分地与所述源极和漏极区重叠的栅极电介质; 形成在栅极电介质上的栅极; 以及在栅极电介质和半导体层之间的掺杂屏蔽层。

7. 发明授权

US08803233B2 Junctionless transistor 有权
标题翻译：无结晶体晶体管
公开(公告)号：US08803233B2
公开(公告)日：2014-08-12
申请号：US13242861
申请日：2011-09-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L29/778
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/1203 , H01L29/78654 , H01L29/78696
摘要： A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.
摘要翻译：晶体管包括半导体层，并且在半导体层上形成栅极电介质。栅极导体形成在栅极电介质上，并且有源区位于栅极电介质下方的半导体层中。有源区包括在半导体层的顶表面附近具有较高掺杂浓度的渐变掺杂区和在半导体层的底表面附近的较低的掺杂浓度。该渐变掺杂剂区域的掺杂浓度逐渐降低。晶体管还包括与有源区相邻的源区和漏区。源极和漏极区域和有源区域具有相同的导电类型。

8. 发明申请

US20130313651A1 INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES 有权
公开(公告)号：US20130313651A1
公开(公告)日：2013-11-28
申请号：US13478080
申请日：2012-05-22
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/07 , H01L21/8238
CPC分类号： H01L27/0629 , H01L29/0847 , H01L29/8611 , H01L29/868
摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

9. 发明授权

US08575698B2 MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation 有权
标题翻译：具有薄半导体通道的MOSFET和具有增强的结隔离的嵌入式应力源
公开(公告)号：US08575698B2
公开(公告)日：2013-11-05
申请号：US13283308
申请日：2011-10-27
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/12
CPC分类号： H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.
摘要翻译：场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。

10. 发明授权

US08564040B1 Inversion mode varactor 有权
标题翻译：反转模式变容二极管
公开(公告)号：US08564040B1
公开(公告)日：2013-10-22
申请号：US13570360
申请日：2012-08-09
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/108
CPC分类号： H01L29/93 , H01L27/1203 , H01L29/66174
摘要： In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：提供具有衬底的倒置模式变容二极管，覆盖衬底的背栅层，覆盖在背栅层上的绝缘层，覆盖绝缘层的半导体层和至少一种金属氧化物半导体场效应晶体管（MOSFET）器件，其设置在所述半导体层上，其中所述半导体层包括源极区和漏极区，其中所述至少一个MOSFET器件包括限定所述源极区和所述漏极区之间的沟道的栅极叠层，其中所述栅极堆叠具有覆盖所述半导体层的栅极介电层和覆盖所述栅极介电层的导电层; 以及向所述背栅层施加偏置电压，以在所述半导体层和所述绝缘层之间的界面处在所述半导体层中形成反转区域。

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