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1. 发明授权

US09041116B2 Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs) 有权
公开(公告)号：US09041116B2
公开(公告)日：2015-05-26
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/092 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

2. 发明申请

US20130313643A1 Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) 有权
标题翻译：用于调制高K金属栅场效应晶体管（FET）的阈值电压的结构和方法
公开(公告)号：US20130313643A1
公开(公告)日：2013-11-28
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/12 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
摘要翻译：一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离存在于第二导电装置区域上的高k栅介质层。连接栅极导体形成在高k栅介质层的第一部分和第二部分上。连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。用含氧气氛曝光改变暴露的半导体器件的阈值电压。

3. 发明申请

US20140024191A1 METHOD OF MULTIPLE PATTERNING TO FORM SEMICONDUCTOR DEVICES 有权
标题翻译：多种图案形成半导体器件的方法
公开(公告)号：US20140024191A1
公开(公告)日：2014-01-23
申请号：US13555240
申请日：2012-07-23
申请人： Kuang-Jung Chen , Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Sen Liu
发明人： Kuang-Jung Chen , Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Sen Liu
IPC分类号： H01L21/31 , H01L21/336
CPC分类号： H01L21/0274 , H01L21/26586 , H01L21/3081 , H01L21/76229 , H01L21/76283 , H01L29/517 , H01L29/66575 , H01L29/78
摘要： A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.
摘要翻译：使用单个掩模和混合光致抗蚀剂形成半导体器件的不同结构的方法。该方法包括：在半导体衬底上施加第一光致抗蚀剂层; 使用光掩模图案化第一光致抗蚀剂层以形成第一图案化光致抗蚀剂层; 使用所述第一图案化的光致抗蚀剂层形成半导体器件的第一结构; 去除第一图案化光致抗蚀剂层; 在所述半导体衬底上施加第二光致抗蚀剂层; 使用光掩模图案化第二光致抗蚀剂层以形成第二图案化光致抗蚀剂层; 使用所述第二图案化的光致抗蚀剂层形成半导体器件的第二结构; 去除第二图案化光致抗蚀剂层; 并且其中所述第一或第二光致抗蚀剂层是包含混合光致抗蚀剂的混合光致抗蚀剂层。

4. 发明授权

US08569868B2 Device having and method for forming fins with multiple widths 有权
标题翻译：具有用于形成多个宽度的翅片的装置和方法
公开(公告)号：US08569868B2
公开(公告)日：2013-10-29
申请号：US13552296
申请日：2012-07-18
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.
摘要翻译：公开了一种用于半导体器件的结构。该结构包括第一特征和第二特征。第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

5. 发明申请

US20120280365A1 DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS 有权
标题翻译：具有形成具有多个宽度的FINS的装置和方法
公开(公告)号：US20120280365A1
公开(公告)日：2012-11-08
申请号：US13552296
申请日：2012-07-18
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.
摘要翻译：公开了一种用于半导体器件的结构。该结构包括第一特征和第二特征。第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

6. 发明授权

US08324036B2 Device having and method for forming fins with multiple widths for an integrated circuit 有权
标题翻译：具有用于形成用于集成电路的多个宽度的散热片的装置和方法
公开(公告)号：US08324036B2
公开(公告)日：2012-12-04
申请号：US12614986
申请日：2009-11-09
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L21/84
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
摘要翻译：一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

7. 发明授权

US08871596B2 Method of multiple patterning to form semiconductor devices 有权
标题翻译：多重图形化形成半导体器件的方法
公开(公告)号：US08871596B2
公开(公告)日：2014-10-28
申请号：US13555240
申请日：2012-07-23
申请人： Kuang-Jung Chen , Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Sen Liu
发明人： Kuang-Jung Chen , Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Sen Liu
IPC分类号： H01L21/31
CPC分类号： H01L21/0274 , H01L21/26586 , H01L21/3081 , H01L21/76229 , H01L21/76283 , H01L29/517 , H01L29/66575 , H01L29/78
摘要： A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.
摘要翻译：使用单个掩模和混合光致抗蚀剂形成半导体器件的不同结构的方法。该方法包括：在半导体衬底上施加第一光致抗蚀剂层; 使用光掩模图案化第一光致抗蚀剂层以形成第一图案化光致抗蚀剂层; 使用所述第一图案化的光致抗蚀剂层形成半导体器件的第一结构; 去除第一图案化光致抗蚀剂层; 在所述半导体衬底上施加第二光致抗蚀剂层; 使用光掩模图案化第二光致抗蚀剂层以形成第二图案化光致抗蚀剂层; 使用所述第二图案化的光致抗蚀剂层形成半导体器件的第二结构; 去除第二图案化光致抗蚀剂层; 并且其中所述第一或第二光致抗蚀剂层是包含混合光致抗蚀剂的混合光致抗蚀剂层。

8. 发明申请

US20110108961A1 DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS 有权
标题翻译：具有形成具有多个宽度的FINS的装置和方法
公开(公告)号：US20110108961A1
公开(公告)日：2011-05-12
申请号：US12614986
申请日：2009-11-09
申请人： KANGGUO CHENG , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： KANGGUO CHENG , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06 , H01L21/302
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
摘要翻译：一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

9. 发明授权

US08803321B2 Dual damascene dual alignment interconnect scheme 有权
标题翻译：双镶嵌双对准互连方案
公开(公告)号：US08803321B2
公开(公告)日：2014-08-12
申请号：US13490542
申请日：2012-06-07
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/535 , H01L21/283
CPC分类号： H01L21/76897 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76819 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76883 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.
摘要翻译：在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。此后形成第二电介质材料层。在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。通过对第一和第二介电材料层的电介质材料的选择性蚀刻去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制的通孔腔，并沿着宽度方向第一条金属线。形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

10. 发明申请

US20130207270A1 DUAL-METAL SELF-ALIGNED WIRES AND VIAS 有权
标题翻译：双金属自对准线和VIAS
公开(公告)号：US20130207270A1
公开(公告)日：2013-08-15
申请号：US13371493
申请日：2012-02-13
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/49
CPC分类号： H01L23/485 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.
摘要翻译：形成半导体结构的方法，包括在半导体衬底上形成第一导电间隔物; 相对于所述第一导电间隔物形成第二导电间隔物，所述第二导电间隔物中的至少一个与所述第一导电间隔物中的每一个相邻并与之接触以形成组合的导电间隔物; 相对于第一导电间隔物使第二导电间隔物凹陷，使得第一导电间隔物延伸超过第二导电间隔物; 沉积ILD以覆盖除了第一导电间隔物的暴露边缘之外的第一和第二间隔物; 图案化第一导电间隔物的暴露边缘以将预定位置中的第一导电间隔物的边缘凹入以形成相对于ILD的凹部; 并用绝缘材料填充凹槽，以将第一导电间隔物的未加工的边缘作为过孔留下以后的布线特征。

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