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1. 发明授权

US08575698B2 MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation 有权
标题翻译：具有薄半导体通道的MOSFET和具有增强的结隔离的嵌入式应力源
公开(公告)号：US08575698B2
公开(公告)日：2013-11-05
申请号：US13283308
申请日：2011-10-27
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/12
CPC分类号： H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.
摘要翻译：场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。

2. 发明授权

US08338260B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08338260B2
公开(公告)日：2012-12-25
申请号：US12760250
申请日：2010-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

3. 发明申请

US20120261754A1 MOSFET with Recessed channel FILM and Abrupt Junctions 有权
标题翻译：具有嵌入式通道FILM和突发接合的MOSFET
公开(公告)号：US20120261754A1
公开(公告)日：2012-10-18
申请号：US13086459
申请日：2011-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0603 , H01L29/1054 , H01L29/4236 , H01L29/66545 , H01L29/66553 , H01L29/66621 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78
摘要： MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.
摘要翻译：公开了用于制造具有凹陷沟道和突然结的MOSFET的MOSFET和方法。该方法包括在虚拟门就位的情况下创建源极和漏极扩展。源极/漏极延伸部分产生与硅衬底的扩散结。该方法通过去除伪栅极并蚀刻硅衬底中的凹槽来继续。凹部与源极和漏极结的至少一部分相交。然后，通过生长硅膜以至少部分地填充凹部而形成通道。该通道与源极和漏极具有尖锐的结，而沟道下方的未蚀刻的硅具有与源极和漏极的扩散结。因此，可以产生在相同晶体管中具有两个结区的尖锐和扩散的MOSFET。

4. 发明申请

US20110316083A1 FET with Self-Aligned Back Gate 有权
标题翻译：具有自对准后门的FET
公开(公告)号：US20110316083A1
公开(公告)日：2011-12-29
申请号：US12823798
申请日：2010-06-25
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/78648
摘要： A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region.
摘要翻译：背栅式场效应晶体管（FET）包括衬底，该衬底包括位于底部半导体层顶部的掩埋电介质层顶部的顶部半导体层; 位于顶部半导体层上的前门; 位于前门下的顶部半导体层中的沟道区; 位于沟道区一侧的顶部半导体层中的源极区域和位于与源极区域相反的沟道区域侧的顶部半导体层中的漏极区域; 以及位于底部半导体层中的背栅，后栅配置成使得后栅极邻接沟道区下方的掩埋介电层，并且在源极区和漏极区之下与掩埋介电层分离距离。

5. 发明授权

US09105577B2 MOSFET with work function adjusted metal backgate 有权
标题翻译：具有工作功能的MOSFET调节金属后盖
公开(公告)号：US09105577B2
公开(公告)日：2015-08-11
申请号：US13398151
申请日：2012-02-16
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/336 , H01L21/265 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/2652 , H01L21/26586 , H01L21/76267 , H01L21/84 , H01L29/45 , H01L29/66772 , H01L29/7831 , H01L29/78648
摘要： An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.
摘要翻译： SOI衬底，半导体器件和背栅功函数调谐方法。衬底和器件具有多个金属背栅区域，其中至少两个区域具有不同的功函数。该方法包括在衬底上形成掩模并且注入置于衬底氧化物和衬底的体区之间的金属背栅，从而产生具有不同剂量的杂质和不同功函数的至少两个金属背栅区。工作功能区域可以对准，使得每个晶体管具有不同的阈值电压。当顶栅电极用作掩模时，形成在沟道区下具有第一功函数的金属背栅和源/漏区下的第二功函数。植入物可以倾斜以相对于掩模移动功函数区域。

6. 发明授权

US08853038B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08853038B2
公开(公告)日：2014-10-07
申请号：US13614572
申请日：2012-09-13
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L21/336 , H01L29/66 , H01L29/786 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack comprises a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A first nitride layer is formed on the silicon layer and the gate stack. An oxide layer is formed on the first nitride layer. A second nitride layer is formed on the oxide layer. The first nitride layer and the oxide layer are etched so as to form a nitride liner and an oxide liner adjacent to the gate stack. The second nitride layer is etched so as to form a first nitride spacer adjacent to the oxide liner. A faceted raised source/drain region is epitaxially formed adjacent to the nitride liner, the oxide liner, and first nitride spacer. Ions are implanted into the faceted raised source/drain region using the first nitride spacer.
摘要翻译：栅极堆叠形成在掩埋氧化物层上方的硅层上。栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。在硅层和栅叠层上形成第一氮化物层。在第一氮化物层上形成氧化物层。在氧化物层上形成第二氮化物层。蚀刻第一氮化物层和氧化物层，以便形成氮化物衬垫和邻近栅叠层的氧化物衬垫。蚀刻第二氮化物层以形成邻近氧化物衬垫的第一氮化物间隔物。与氮化物衬垫，氧化物衬垫和第一氮化物间隔物相邻地外延形成刻面隆起的源极/漏极区。使用第一氮化物间隔物将离子植入到刻面隆起的源极/漏极区域中。

7. 发明申请

US20130214356A1 MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE 有权
公开(公告)号：US20130214356A1
公开(公告)日：2013-08-22
申请号：US13398151
申请日：2012-02-16
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/088 , H01L21/265
CPC分类号： H01L27/1203 , H01L21/2652 , H01L21/26586 , H01L21/76267 , H01L21/84 , H01L29/45 , H01L29/66772 , H01L29/7831 , H01L29/78648
摘要： An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.

8. 发明授权

US08421156B2 FET with self-aligned back gate 有权
标题翻译：具有自对准背栅的FET
公开(公告)号：US08421156B2
公开(公告)日：2013-04-16
申请号：US12823798
申请日：2010-06-25
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/66 , H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/78648
摘要： A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region.
摘要翻译：背栅式场效应晶体管（FET）包括衬底，该衬底包括位于底部半导体层顶部的掩埋电介质层顶部的顶部半导体层; 位于顶部半导体层上的前门; 位于前门下的顶部半导体层中的沟道区; 位于沟道区一侧的顶部半导体层中的源极区域和位于与源极区域相反的沟道区域侧的顶部半导体层中的漏极区域; 以及位于底部半导体层中的背栅，后栅配置成使得后栅极邻接沟道区下方的掩埋介质层，并且在源极区和漏极区之下与掩埋介电层分离距离。

9. 发明授权

US08890245B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08890245B2
公开(公告)日：2014-11-18
申请号：US13570833
申请日：2012-08-09
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L29/78 , H01L29/786 , H01L29/66 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

10. 发明授权

US08691650B2 MOSFET with recessed channel film and abrupt junctions 有权
标题翻译：具有凹槽通道膜和突点的MOSFET
公开(公告)号：US08691650B2
公开(公告)日：2014-04-08
申请号：US13086459
申请日：2011-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/336
CPC分类号： H01L29/0603 , H01L29/1054 , H01L29/4236 , H01L29/66545 , H01L29/66553 , H01L29/66621 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78
摘要： MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.
摘要翻译：公开了用于制造具有凹陷沟道和突然结的MOSFET的MOSFET和方法。该方法包括在虚拟门就位的情况下创建源极和漏极扩展。源极/漏极延伸部分产生与硅衬底的扩散结。该方法通过去除伪栅极并蚀刻硅衬底中的凹槽来继续。凹部与源极和漏极结的至少一部分相交。然后，通过生长硅膜以至少部分地填充凹部而形成通道。该通道与源极和漏极具有尖锐的结，而沟道下方的未蚀刻的硅具有与源极和漏极的扩散结。因此，可以产生在相同晶体管中具有两个结区的尖锐和扩散的MOSFET。

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