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1. 发明授权

US09425112B2 Calibration kits for RF passive devices 有权
标题翻译： RF无源器件校准套件
公开(公告)号：US09425112B2
公开(公告)日：2016-08-23
申请号：US13491364
申请日：2012-06-07
申请人： Jie Chen , Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo
发明人： Jie Chen , Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo
IPC分类号： G06F17/00 , G06F17/50 , H01L23/48 , H01L21/66 , H01L21/768 , H01L23/522 , H01L49/02
CPC分类号： H01L23/66 , G01R1/07328 , G01R35/005 , G06F17/5009 , H01L21/76822 , H01L22/34 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L24/13 , H01L28/10 , H01L2223/6627 , H01L2224/0401 , H01L2224/131 , H01L2224/13147 , H01L2924/19011 , H01L2924/1903 , H01L2924/19042 , H01L2924/00014 , H01L2924/014
摘要： A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices.
摘要翻译：一种方法包括测量晶片中的第一校准套件以获得第一性能数据。晶片包括衬底，以及在衬底上的多个电介质层。第一校准套件包括多个电介质层上的第一无源器件，其中在多个电介质层中基本上没有金属特征被布置在第一无源器件中。该方法还包括测量晶片中的第二校准套件以获得第二性能数据。第二校准套件包括与第一器件相同并且在多个电介质层上相同的第二无源器件，以及多个电介质层中的虚设图案并且被第二无源器件重叠。第一性能数据和第二性能数据被去嵌入以确定多个介电层中的金属图案对覆盖无源器件的影响。

2. 发明申请

US20130332092A1 Calibration Kits for RF Passive Devices 有权
标题翻译： RF被动设备的校准套件
公开(公告)号：US20130332092A1
公开(公告)日：2013-12-12
申请号：US13491364
申请日：2012-06-07
申请人： Jie Chen , Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo
发明人： Jie Chen , Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo
IPC分类号： G06F19/00 , G06F17/50 , H01L23/48
CPC分类号： H01L23/66 , G01R1/07328 , G01R35/005 , G06F17/5009 , H01L21/76822 , H01L22/34 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L24/13 , H01L28/10 , H01L2223/6627 , H01L2224/0401 , H01L2224/131 , H01L2224/13147 , H01L2924/19011 , H01L2924/1903 , H01L2924/19042 , H01L2924/00014 , H01L2924/014
摘要： A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices.
摘要翻译：一种方法包括测量晶片中的第一校准套件以获得第一性能数据。晶片包括衬底，以及在衬底上的多个电介质层。第一校准套件包括多个电介质层上的第一无源器件，其中在多个电介质层中基本上没有金属特征被布置在第一无源器件中。该方法还包括测量晶片中的第二校准套件以获得第二性能数据。第二校准套件包括与第一器件相同并且在多个电介质层上相同的第二无源器件，以及多个电介质层中的虚设图案并且被第二无源器件重叠。第一性能数据和第二性能数据被去嵌入以确定多个介电层中的金属图案对覆盖无源器件的影响。

3. 发明申请

US20130241683A1 Inductor for Post Passivation Interconnect 有权
标题翻译：后钝化互感器电感
公开(公告)号：US20130241683A1
公开(公告)日：2013-09-19
申请号：US13419272
申请日：2012-03-13
申请人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
发明人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
IPC分类号： H01F5/00 , H01F41/02
CPC分类号： H01L23/5227 , H01L21/768 , H01L23/5225 , H01L23/552 , H01L23/585 , H01L24/03 , H01L24/11 , H01L28/10 , H01L2224/02351 , H01L2224/0401 , H01L2224/06515 , Y10T29/4902
摘要： An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
摘要翻译：提供一种形成电感器件的电感器件和方法。在一些实施例中，电感器件包括设置在衬底上的后钝化互连（PPI）层和凸块下金属化（UBM）层。 PPI层形成线圈和虚拟垫。虚拟焊盘围绕线圈的大部分设置，以屏蔽线圈免受电磁干扰。 UBM层的第一部分电耦合到线圈并且被配置为与电耦合构件相接合。

4. 发明授权

US09000876B2 Inductor for post passivation interconnect 有权
标题翻译：后钝化互连电感
公开(公告)号：US09000876B2
公开(公告)日：2015-04-07
申请号：US13419272
申请日：2012-03-13
申请人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
发明人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
IPC分类号： H01F5/00 , H01F27/28 , H01F27/36 , H01L31/107 , H01L23/522 , H01L23/552 , H01L23/00 , H01L49/02 , H01L23/58
CPC分类号： H01L23/5227 , H01L21/768 , H01L23/5225 , H01L23/552 , H01L23/585 , H01L24/03 , H01L24/11 , H01L28/10 , H01L2224/02351 , H01L2224/0401 , H01L2224/06515 , Y10T29/4902
摘要： An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
摘要翻译：提供一种形成电感器件的电感器件和方法。在一些实施例中，电感器件包括设置在衬底上的后钝化互连（PPI）层和凸块下金属化（UBM）层。 PPI层形成线圈和虚拟垫。虚拟焊盘围绕线圈的大部分设置，以屏蔽线圈免受电磁干扰。 UBM层的第一部分电耦合到线圈并且被配置为与电耦合构件相接合。

5. 发明授权

US09349655B2 Method for mechanical stress enhancement in semiconductor devices 有权
标题翻译：半导体器件中的机械应力增强方法
公开(公告)号：US09349655B2
公开(公告)日：2016-05-24
申请号：US12391821
申请日：2009-02-24
申请人： Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
发明人： Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
IPC分类号： H01L21/70 , H01L21/8238 , H01L27/02 , H01L29/165 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823828 , H01L27/0207 , H01L29/165 , H01L29/66628 , H01L29/7848
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.
摘要翻译：本发明提供集成电路。集成电路包括具有有源区的半导体衬底; 所述活动区域上的至少一个操作装置，其中所述操作装置包括应变通道; 以及设置在所述操作装置的一侧和所述有源区域上的至少一个第一伪栅极。

6. 发明授权

US08669651B2 Package-on-package structures with reduced bump bridging 有权
标题翻译：封装封装结构，减少桥接桥接
公开(公告)号：US08669651B2
公开(公告)日：2014-03-11
申请号：US12843549
申请日：2010-07-26
申请人： Chung-Ying Yang , Chao-Wen Shih , Hao-Yi Tsai , Hsien-Wei Chen , Mirng-Ji Lii , Tzuan-Horng Liu
发明人： Chung-Ying Yang , Chao-Wen Shih , Hao-Yi Tsai , Hsien-Wei Chen , Mirng-Ji Lii , Tzuan-Horng Liu
IPC分类号： H01L23/538
CPC分类号： H01L23/5385 , H01L23/3121 , H01L23/5384 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/32225 , H01L2224/451 , H01L2224/48227 , H01L2224/73204 , H01L2225/0651 , H01L2225/06517 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A device includes a package substrate including a first non-reflowable metal bump extending over a top surface of the package substrate; a die over and bonded to the package substrate; and a package component over the die and bonded to the package substrate. The package component includes a second non-reflowable metal bump extending below a bottom surface of the package component. The package component is selected from the group consisting essentially of a device die, an additional package substrate, and combinations thereof. A solder bump bonds the first non-reflowable metal bump to the second non-reflowable metal bump.
摘要翻译：一种器件包括封装衬底，其包括在封装衬底的顶表面上延伸的第一不可回流金属凸块; 并且结合到封装基板上; 以及在所述管芯上并且结合到所述封装衬底的封装部件。包装部件包括在包装部件的底部表面下方延伸的第二不可回流金属凸块。封装部件选自基本上由器件管芯，附加封装衬底及其组合组成的组。焊料凸块将第一不可回流金属凸块接合到第二不可回流金属凸块。

7. 发明授权

US08618827B2 Measurement of electrical and mechanical characteristics of low-K dielectric in a semiconductor device 有权
标题翻译：半导体器件中低K电介质的电气和机械特性的测量
公开(公告)号：US08618827B2
公开(公告)日：2013-12-31
申请号：US12903984
申请日：2010-10-13
申请人： Tung-Liang Shao , Shih-Wei Liang , Ying-Ju Chen , Ching-Jung Yang , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii , Chen-Hua Yu
发明人： Tung-Liang Shao , Shih-Wei Liang , Ying-Ju Chen , Ching-Jung Yang , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2648 , G01R31/002 , G01R31/2644 , G01R31/2884 , H01L22/34 , H01L2224/13
摘要： Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.
摘要翻译：提供了一种用于测试未封装的半导体晶片的测试结构。测试结构包括耦合到半导体晶片的互连结构的施力部件。力施加部件可操作以向半导体晶片施加力。测试结构还包括耦合到互连结构的第一和第二测试部分。第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

8. 发明授权

US08334582B2 Protective seal ring for preventing die-saw induced stress 有权
标题翻译：用于防止模锯引起的应力的保护密封环
公开(公告)号：US08334582B2
公开(公告)日：2012-12-18
申请号：US12347026
申请日：2008-12-31
申请人： Shin-Puu Jeng , Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu , Yu-Wen Liu
发明人： Shin-Puu Jeng , Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu , Yu-Wen Liu
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.
摘要翻译：半导体芯片包括半导体衬底; 半导体衬底上的多个低k电介质层; 在所述多个低k电介质层上的第一钝化层; 以及在所述第一钝化层上的第二钝化层。第一密封环邻近半导体芯片的边缘，其中第一密封环具有基本上平坦于第一钝化层的底表面的上表面。第二密封环与第一密封环相邻，并且在半导体芯片的内侧与第一密封环相邻。第二密封环包括在第一钝化层和第二钝化层中的焊盘环。沟槽环包括直接在第一密封环上的至少一部分。沟槽环从第二钝化层的顶表面延伸到至少第一钝化层和第二钝化层之间的界面。

9. 发明授权

US08278737B2 Structure for improving die saw quality 有权
标题翻译：提高模锯质量的结构
公开(公告)号：US08278737B2
公开(公告)日：2012-10-02
申请号：US12417394
申请日：2009-04-02
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Ying-Ju Chen , Yu-Wen Liu , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Ying-Ju Chen , Yu-Wen Liu , Shin-Puu Jeng
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6.
摘要翻译：提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底上的多个管芯，所述多个管芯沿着第一方向延伸的第一区域彼此分离，并且沿着不同于第二方向的第二方向延伸的第二区域第一方向，形成在第三区域内的虚设金属结构，所述第三区域包括由所述第一区域和所述第二区域的交点限定的区域，形成在所述基板上的多个金属互连层，以及形成在所述第二区域上的多个电介质层基质。每个金属互连层设置在每个介电层内，并且至少一个电介质层的介电常数小于约2.6。

10. 发明授权

US08178980B2 Bond pad structure 有权
标题翻译：焊盘结构
公开(公告)号：US08178980B2
公开(公告)日：2012-05-15
申请号：US12026312
申请日：2008-02-05
申请人： Shin-Puu Jeng , Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen
发明人： Shin-Puu Jeng , Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen
IPC分类号： H01L29/40
CPC分类号： H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/0401 , H01L2224/05093 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05552 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/16 , H01L2224/85201 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01049 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01087 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/30105 , H01L2924/3011 , H01L2924/37001 , H01L2924/00012 , H01L2924/00
摘要： A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. In an embodiment, the conductive density of the connective layer is between approximately 20% and 100%.
摘要翻译：提供了一种焊盘结构，其包括两个导电层和插入两个导电层的连接层。连接层包括连续的导电结构。在一个实施例中，邻接的导电结构是导电材料的固体层。在其它实施例中，连续导电结构是包括例如矩阵配置或多个导电条纹的导电网络。至少一个电介质间隔物可以插入导电网络。在一个实施例中，连接层的导电密度在大约20％和100％之间。

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