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1. 发明授权

US09000876B2 Inductor for post passivation interconnect 有权
标题翻译：后钝化互连电感
公开(公告)号：US09000876B2
公开(公告)日：2015-04-07
申请号：US13419272
申请日：2012-03-13
申请人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
发明人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
IPC分类号： H01F5/00 , H01F27/28 , H01F27/36 , H01L31/107 , H01L23/522 , H01L23/552 , H01L23/00 , H01L49/02 , H01L23/58
CPC分类号： H01L23/5227 , H01L21/768 , H01L23/5225 , H01L23/552 , H01L23/585 , H01L24/03 , H01L24/11 , H01L28/10 , H01L2224/02351 , H01L2224/0401 , H01L2224/06515 , Y10T29/4902
摘要： An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
摘要翻译：提供一种形成电感器件的电感器件和方法。在一些实施例中，电感器件包括设置在衬底上的后钝化互连（PPI）层和凸块下金属化（UBM）层。 PPI层形成线圈和虚拟垫。虚拟焊盘围绕线圈的大部分设置，以屏蔽线圈免受电磁干扰。 UBM层的第一部分电耦合到线圈并且被配置为与电耦合构件相接合。

2. 发明申请

US20130241683A1 Inductor for Post Passivation Interconnect 有权
标题翻译：后钝化互感器电感
公开(公告)号：US20130241683A1
公开(公告)日：2013-09-19
申请号：US13419272
申请日：2012-03-13
申请人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
发明人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
IPC分类号： H01F5/00 , H01F41/02
CPC分类号： H01L23/5227 , H01L21/768 , H01L23/5225 , H01L23/552 , H01L23/585 , H01L24/03 , H01L24/11 , H01L28/10 , H01L2224/02351 , H01L2224/0401 , H01L2224/06515 , Y10T29/4902
摘要： An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
摘要翻译：提供一种形成电感器件的电感器件和方法。在一些实施例中，电感器件包括设置在衬底上的后钝化互连（PPI）层和凸块下金属化（UBM）层。 PPI层形成线圈和虚拟垫。虚拟焊盘围绕线圈的大部分设置，以屏蔽线圈免受电磁干扰。 UBM层的第一部分电耦合到线圈并且被配置为与电耦合构件相接合。

3. 发明授权

US09425112B2 Calibration kits for RF passive devices 有权
标题翻译： RF无源器件校准套件
公开(公告)号：US09425112B2
公开(公告)日：2016-08-23
申请号：US13491364
申请日：2012-06-07
申请人： Jie Chen , Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo
发明人： Jie Chen , Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo
IPC分类号： G06F17/00 , G06F17/50 , H01L23/48 , H01L21/66 , H01L21/768 , H01L23/522 , H01L49/02
CPC分类号： H01L23/66 , G01R1/07328 , G01R35/005 , G06F17/5009 , H01L21/76822 , H01L22/34 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L24/13 , H01L28/10 , H01L2223/6627 , H01L2224/0401 , H01L2224/131 , H01L2224/13147 , H01L2924/19011 , H01L2924/1903 , H01L2924/19042 , H01L2924/00014 , H01L2924/014
摘要： A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices.
摘要翻译：一种方法包括测量晶片中的第一校准套件以获得第一性能数据。晶片包括衬底，以及在衬底上的多个电介质层。第一校准套件包括多个电介质层上的第一无源器件，其中在多个电介质层中基本上没有金属特征被布置在第一无源器件中。该方法还包括测量晶片中的第二校准套件以获得第二性能数据。第二校准套件包括与第一器件相同并且在多个电介质层上相同的第二无源器件，以及多个电介质层中的虚设图案并且被第二无源器件重叠。第一性能数据和第二性能数据被去嵌入以确定多个介电层中的金属图案对覆盖无源器件的影响。

4. 发明申请

US20130332092A1 Calibration Kits for RF Passive Devices 有权
标题翻译： RF被动设备的校准套件
公开(公告)号：US20130332092A1
公开(公告)日：2013-12-12
申请号：US13491364
申请日：2012-06-07
申请人： Jie Chen , Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo
发明人： Jie Chen , Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo
IPC分类号： G06F19/00 , G06F17/50 , H01L23/48
CPC分类号： H01L23/66 , G01R1/07328 , G01R35/005 , G06F17/5009 , H01L21/76822 , H01L22/34 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L24/13 , H01L28/10 , H01L2223/6627 , H01L2224/0401 , H01L2224/131 , H01L2224/13147 , H01L2924/19011 , H01L2924/1903 , H01L2924/19042 , H01L2924/00014 , H01L2924/014
摘要： A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices.
摘要翻译：一种方法包括测量晶片中的第一校准套件以获得第一性能数据。晶片包括衬底，以及在衬底上的多个电介质层。第一校准套件包括多个电介质层上的第一无源器件，其中在多个电介质层中基本上没有金属特征被布置在第一无源器件中。该方法还包括测量晶片中的第二校准套件以获得第二性能数据。第二校准套件包括与第一器件相同并且在多个电介质层上相同的第二无源器件，以及多个电介质层中的虚设图案并且被第二无源器件重叠。第一性能数据和第二性能数据被去嵌入以确定多个介电层中的金属图案对覆盖无源器件的影响。

5. 发明授权

US09129816B2 Contact test structure and method 有权
标题翻译：接触测试结构和方法
公开(公告)号：US09129816B2
公开(公告)日：2015-09-08
申请号：US13422846
申请日：2012-03-16
申请人： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen
发明人： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen
IPC分类号： H01L21/66 , H01L23/00 , H01L23/482
CPC分类号： H01L22/34 , H01L22/30 , H01L22/32 , H01L23/4824 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05008 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05569 , H01L2224/05572 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/0603 , H01L2224/06179 , H01L2224/06505 , H01L2224/11015 , H01L2224/13006 , H01L2224/13022 , H01L2224/13026 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14153 , H01L2224/14155 , H01L2924/01029 , H01L2924/00014 , H01L2924/207 , H01L2924/014
摘要： A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.
摘要翻译：提供了一种用于测试电气连接的系统和方法。在一个实施例中，可以制造一个或多个浮动焊盘，以与下部焊接金属化结构电连接。然后可以进行测试以通过浮动垫测量底部金属化结构的电特性，以测试缺陷。或者，可以在下凸点金属化上形成导电连接，并且可以在导电连接和下凸点金属化一起进行测试。

6. 发明申请

US20130240883A1 Contact Test Structure and Method 有权
公开(公告)号：US20130240883A1
公开(公告)日：2013-09-19
申请号：US13422846
申请日：2012-03-16
申请人： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen
发明人： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L22/34 , H01L22/30 , H01L22/32 , H01L23/4824 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05008 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05569 , H01L2224/05572 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/0603 , H01L2224/06179 , H01L2224/06505 , H01L2224/11015 , H01L2224/13006 , H01L2224/13022 , H01L2224/13026 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14153 , H01L2224/14155 , H01L2924/01029 , H01L2924/00014 , H01L2924/207 , H01L2924/014
摘要： A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

7. 发明授权

US08618827B2 Measurement of electrical and mechanical characteristics of low-K dielectric in a semiconductor device 有权
标题翻译：半导体器件中低K电介质的电气和机械特性的测量
公开(公告)号：US08618827B2
公开(公告)日：2013-12-31
申请号：US12903984
申请日：2010-10-13
申请人： Tung-Liang Shao , Shih-Wei Liang , Ying-Ju Chen , Ching-Jung Yang , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii , Chen-Hua Yu
发明人： Tung-Liang Shao , Shih-Wei Liang , Ying-Ju Chen , Ching-Jung Yang , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2648 , G01R31/002 , G01R31/2644 , G01R31/2884 , H01L22/34 , H01L2224/13
摘要： Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.
摘要翻译：提供了一种用于测试未封装的半导体晶片的测试结构。测试结构包括耦合到半导体晶片的互连结构的施力部件。力施加部件可操作以向半导体晶片施加力。测试结构还包括耦合到互连结构的第一和第二测试部分。第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

8. 发明授权

US08278737B2 Structure for improving die saw quality 有权
标题翻译：提高模锯质量的结构
公开(公告)号：US08278737B2
公开(公告)日：2012-10-02
申请号：US12417394
申请日：2009-04-02
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Ying-Ju Chen , Yu-Wen Liu , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Ying-Ju Chen , Yu-Wen Liu , Shin-Puu Jeng
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6.
摘要翻译：提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底上的多个管芯，所述多个管芯沿着第一方向延伸的第一区域彼此分离，并且沿着不同于第二方向的第二方向延伸的第二区域第一方向，形成在第三区域内的虚设金属结构，所述第三区域包括由所述第一区域和所述第二区域的交点限定的区域，形成在所述基板上的多个金属互连层，以及形成在所述第二区域上的多个电介质层基质。每个金属互连层设置在每个介电层内，并且至少一个电介质层的介电常数小于约2.6。

9. 发明申请

US20100117080A1 SEMICONDUCTOR TEST PAD STRUCTURES 有权
公开(公告)号：US20100117080A1
公开(公告)日：2010-05-13
申请号：US12267021
申请日：2008-11-07
申请人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： H01L23/485
CPC分类号： H01L22/34 , H01L24/05 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
摘要翻译：具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。在其他实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

10. 发明申请

US20090283911A1 Backend Interconnect Scheme with Middle Dielectric Layer Having Improved Strength 有权
标题翻译：后置互连方案与中间介质层具有改进的强度
公开(公告)号：US20090283911A1
公开(公告)日：2009-11-19
申请号：US12121541
申请日：2008-05-15
申请人： Hao-Yi Tsai , Yu-Wen Liu , Hsien-Wei Chen , Ying-Ju Chen , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Yu-Wen Liu , Hsien-Wei Chen , Ying-Ju Chen , Shin-Puu Jeng
IPC分类号： H01L23/522
CPC分类号： H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05556 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a second dielectric layer having a second k value greater than the first k value; and second metal lines in the second dielectric layer. The third metallization layer is over the second metallization layer, and includes a third dielectric layer having a third k value; and third metal lines in the third dielectric layer. The integrated circuit structure further includes a bottom passivation layer over the third metallization layer.
摘要翻译：集成电路结构包括第一，第二和第三金属化层。第一金属化层包括具有第一k值的第一介电层; 和第一介电层中的第一金属线。第二金属化层在第一金属化层之上，并且包括具有大于第一k值的第二k值的第二介电层; 和第二介电层中的第二金属线。第三金属化层在第二金属化层之上，并且包括具有第三k值的第三介电层; 和第三介电层中的第三金属线。集成电路结构还包括在第三金属化层上的底部钝化层。

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