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1. 发明授权

US09349655B2 Method for mechanical stress enhancement in semiconductor devices 有权
标题翻译：半导体器件中的机械应力增强方法
公开(公告)号：US09349655B2
公开(公告)日：2016-05-24
申请号：US12391821
申请日：2009-02-24
申请人： Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
发明人： Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
IPC分类号： H01L21/70 , H01L21/8238 , H01L27/02 , H01L29/165 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823828 , H01L27/0207 , H01L29/165 , H01L29/66628 , H01L29/7848
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.
摘要翻译：本发明提供集成电路。集成电路包括具有有源区的半导体衬底; 所述活动区域上的至少一个操作装置，其中所述操作装置包括应变通道; 以及设置在所述操作装置的一侧和所述有源区域上的至少一个第一伪栅极。

2. 发明授权

US09142414B2 CMOS devices with metal gates and methods for forming the same 有权
标题翻译：具有金属栅极的CMOS器件及其形成方法
公开(公告)号：US09142414B2
公开(公告)日：2015-09-22
申请号：US13331214
申请日：2011-12-20
申请人： Sheng-Chen Chung , Ming Zhu , Harry-Hak-Lay Chuang , Bao-Ru Young , Wei-Cheng Wu , Chia Ming Liang , Sin-Hua Wu
发明人： Sheng-Chen Chung , Ming Zhu , Harry-Hak-Lay Chuang , Bao-Ru Young , Wei-Cheng Wu , Chia Ming Liang , Sin-Hua Wu
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78
CPC分类号： H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.
摘要翻译：一种方法包括形成PMOS器件。该方法包括在半导体衬底和PMOS区域上形成栅极电介质层，在栅极电介质层和PMOS区域上形成第一含金属层，对PMOS区域中的第一含金属层进行处理使用含氧处理气体，并在第一含金属层和PMOS区域上形成第二含金属层。第二含金属层具有低于硅的中间间隙功函数的功函数。第一含金属层和第二含金属层形成PMOS器件的栅极。

3. 发明授权

US08368136B2 Integrating a capacitor in a metal gate last process 有权
标题翻译：将电容器集成在金属栅极最后工艺中
公开(公告)号：US08368136B2
公开(公告)日：2013-02-05
申请号：US12256132
申请日：2008-10-22
申请人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
发明人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
IPC分类号： H01L27/04
CPC分类号： H01L27/0629 , H01L27/11 , H01L29/94
摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料电极。

4. 发明授权

US08329521B2 Method and device with gate structure formed over the recessed top portion of the isolation structure 有权
标题翻译：具有栅极结构的方法和装置形成在隔离结构的凹入的顶部上
公开(公告)号：US08329521B2
公开(公告)日：2012-12-11
申请号：US12830107
申请日：2010-07-02
申请人： Harry Hak-Lay Chuang , Bao-Ru Young , Sheng-Chen Chung , Kai-Shyang You , Jin-Aun Ng , Wei Cheng Wu , Ming Zhu
发明人： Harry Hak-Lay Chuang , Bao-Ru Young , Sheng-Chen Chung , Kai-Shyang You , Jin-Aun Ng , Wei Cheng Wu , Ming Zhu
IPC分类号： H01L21/8238 , H01L27/148
CPC分类号： H01L21/823481 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L29/66545
摘要： A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.
摘要翻译：一种方法包括提供具有第一表面的基板，形成部分地设置在基板中的隔离结构，并且具有高于第一表面的台阶高度的第二表面，去除隔离结构的一部分以形成其中具有底部表面与所述第一表面间隔开小于所述台阶高度，形成栅极结构，以及形成在所述凹部上接合所述栅极结构的触点。不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有与所述第一表面间隔小于所述台阶高度的底表面，栅极结构以及在所述凹部上接合所述栅极结构的触点。

5. 发明申请

US20110059601A1 METHOD FOR TUNING A WORK FUNCTION OF HIGH-K METAL GATE DEVICES 有权
标题翻译：用于调谐高K金属栅极器件功能的方法
公开(公告)号：US20110059601A1
公开(公告)日：2011-03-10
申请号：US12944221
申请日：2010-11-11
申请人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/768 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/517 , H01L29/66545
摘要： A method of fabricating a semiconductor device includes forming a first trench and a second trench on a semiconductor substrate and forming a first metal layer in the first and second trenches. The first metal layer is then removed, at least partially, from within the first trench but not the second trench. A second metal layer and a third metal layer are formed in the first and second trenches. A thermal process is used to reflow the second metal layer and the third metal layer
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成第一沟槽和第二沟槽，并在第一和第二沟槽中形成第一金属层。然后至少部分地从第一沟槽内除去第一金属层而不是第二沟槽。在第一和第二沟槽中形成第二金属层和第三金属层。使用热处理来回流第二金属层和第三金属层

6. 发明申请

US20100117190A1 FUSE STRUCTURE FOR INTERGRATED CIRCUIT DEVICES 审中-公开
标题翻译：用于集成电路设备的保险丝结构
公开(公告)号：US20100117190A1
公开(公告)日：2010-05-13
申请号：US12270717
申请日：2008-11-13
申请人： Harry CHUANG , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
发明人： Harry CHUANG , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for an IC device and methods of fabricating the structure are provided. The fuse structure comprises a metal-containing conductive strip formed over a portion of a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate, covering the conductive strip. A first interconnect and a second interconnect are formed in vias extending through the dielectric layer, each physically and electrically connecting to a part of the conductive layer. First and second wiring structures are formed over the dielectric layer in electrical contact with the first and second interconnects respectively. The contact area between one of the interconnects and the strip is chosen so that electromigration will occur when a pre-selected current is applied to the fuse structure.
摘要翻译：提供了一种用于IC器件的熔丝结构及其制造方法。熔丝结构包括在半导体衬底的一部分上形成的含金属的导电条。在半导体衬底上形成介电层，覆盖导电带。第一互连和第二互连形成在延伸穿过介电层的通孔中，每个物理和电连接到导电层的一部分。第一和第二布线结构形成在电介质层上，分别与第一和第二互连电接触。选择互连和条之一之间的接触面积，使得当将预选电流施加到熔丝结构时，将发生电迁移。

7. 发明申请

US20100087038A1 METHOD FOR N/P PATTERNING IN A GATE LAST PROCESS 有权
标题翻译：用于门窗最后过程中N / P图案的方法
公开(公告)号：US20100087038A1
公开(公告)日：2010-04-08
申请号：US12364384
申请日：2009-02-02
申请人： Sheng-Chen CHUNG , Kong-Beng THEI , Harry CHUANG
发明人： Sheng-Chen CHUNG , Kong-Beng THEI , Harry CHUANG
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28052 , H01L21/28088 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A method is provided that includes providing a substrate, forming a first gate structure in a first region and a second gate structure in a second region, the first and second gate structures each including a high-k dielectric layer, a silicon layer, and a hard mask layer, where the silicon layer of the first gate structure has a different thickness than the silicon layer of the second gate structure, forming an interlayer dielectric (ILD) over the first and second gate structures, performing a chemical mechanical polishing (CMP) on the ILD, removing the silicon layer from the first gate structure thereby forming a first trench, forming a first metal layer to fill in the first trench, removing the hard mask layer and the silicon layer from the second gate structure thereby forming a second trench, and forming a second metal layer to fill in the second trench.
摘要翻译：提供了一种方法，其包括提供衬底，在第一区域中形成第一栅极结构和在第二区域中形成第二栅极结构，所述第一和第二栅极结构各自包括高k电介质层，硅层和硬掩模层，其中第一栅极结构的硅层具有与第二栅极结构的硅层不同的厚度，在第一和第二栅极结构上形成层间电介质（ILD），执行化学机械抛光（CMP）在所述ILD上，从所述第一栅极结构去除所述硅层，从而形成第一沟槽，形成第一金属层以填充所述第一沟槽，从所述第二栅极结构去除所述硬掩模层和所述硅层，由此形成第二沟槽并且形成第二金属层以填充第二沟槽。

8. 发明申请

US20100068877A1 METHOD FOR TUNING A WORK FUNCTION OF HIGH-K METAL GATE DEVICES 有权
标题翻译：用于调谐高K金属栅极器件功能的方法
公开(公告)号：US20100068877A1
公开(公告)日：2010-03-18
申请号：US12488960
申请日：2009-06-22
申请人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Chiung-Han Yeh , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming first and second transistors in the substrate, the first transistor having a first gate structure that includes a first dummy gate, the second transistor having a second gate structure that includes a second dummy gate, removing the first and second dummy gates thereby forming a first trench and a second trench, respectively, forming a first metal layer to partially fill in the first and second trenches, removing the first metal layer within the first trench, forming a second metal layer to partially fill in the first and second trenches, forming a third metal layer to partially fill in the first and second trenches, reflowing the second metal layer and the third metal layer, and forming a fourth metal layer to fill in the remainder of the first and second trenches.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底中形成第一和第二晶体管，第一晶体管具有包括第一虚拟栅极的第一栅极结构，第二晶体管具有第二栅极结构包括第二伪栅极，去除第一和第二伪栅极，从而分别形成第一沟槽和第二沟槽，形成第一金属层以部分地填充在第一和第二沟槽中，去除第一沟槽内的第一金属层形成第二金属层以部分地填充在第一和第二沟槽中，形成第三金属层以部分地填充在第一和第二沟槽中，回流第二金属层和第三金属层，以及形成第四金属层以填充在第一和第二个沟槽的剩余部分。

9. 发明申请

US20100062577A1 HIGH-K METAL GATE STRUCTURE FABRICATION METHOD INCLUDING HARD MASK 有权
标题翻译：高K金属结构制造方法，包括硬掩模
公开(公告)号：US20100062577A1
公开(公告)日：2010-03-11
申请号：US12270466
申请日：2008-11-13
申请人： Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Provided is a method of fabricating a semiconductor device including a high-k metal gate structure. A substrate is provided including a dummy gate structure (e.g., a sacrificial polysilicon gate), a first and second hard mask layer overlie the dummy gate structure. In one embodiment, a strained region is formed on the substrate. After forming the strained region, the second hard mask layer may be removed. A source/drain region may be formed. An ILD layer is then formed on the substrate. A CMP process may planarize the ILD layer using the first hard mask layer as a stop layer. The CMP process may be continued to remove the first hard mask layer. The dummy gate structure is then removed and a metal gate provided.
摘要翻译：提供一种制造包括高k金属栅极结构的半导体器件的方法。提供了包括伪栅极结构（例如，牺牲多晶硅栅极），覆盖在虚拟栅极结构上的第一和第二硬掩模层的衬底。在一个实施例中，在基底上形成应变区域。形成应变区后，可以除去第二硬掩模层。可以形成源极/漏极区域。然后在衬底上形成ILD层。 CMP工艺可以使用第一硬掩模层作为停止层来平坦化ILD层。 CMP工艺可以继续去除第一硬掩模层。然后去除虚拟栅极结构并提供金属栅极。

10. 发明申请

US20090298243A1 SOI DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译： SOI器件及其制造方法
公开(公告)号：US20090298243A1
公开(公告)日：2009-12-03
申请号：US12468131
申请日：2009-05-19
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
摘要翻译：提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。在衬底上形成第一绝缘层。在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。第一电介质层形成在每个半导体岛的一部分上。导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

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