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1. 发明申请

US20090173994A1 RECESS GATE TRANSISTOR 有权
标题翻译：记忆闸门晶体管
公开(公告)号：US20090173994A1
公开(公告)日：2009-07-09
申请号：US12251054
申请日：2008-10-14
申请人： Ji-Young Min , Si-Hyung Lee , Heedon Hwang , Si-Young Choi , Sangbom Kang , Dongsoo Woo
发明人： Ji-Young Min , Si-Hyung Lee , Heedon Hwang , Si-Young Choi , Sangbom Kang , Dongsoo Woo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66553 , H01L21/28079 , H01L21/28114 , H01L29/4236
摘要： A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.
摘要翻译：提供半导体器件的凹槽，其包括：形成有凹部的基板; 形成在所述凹部的底部的金属层; 形成在所述金属层上的多晶硅层; 以及与所述多晶硅层相邻形成并与所述金属层隔开形成的源极区域和漏极区域。还提供了一种形成半导体器件的方法，包括形成衬底和源极和漏极层; 形成凹部并在其中沉积栅极绝缘层; 在所述栅绝缘层上形成第一导电层; 通过使所述第一导电层凹陷来形成第一导电层图案; 在所述第一导电层图案上形成第二导电层; 通过图案化所述第二导电层以与所述源极和漏极层重叠而形成第二导电层图案; 在第二导电层图案和源极和漏极层上沉积绝缘层; 并且平坦化绝缘层以在第二导电层图案上形成帽。

2. 发明授权

US08012828B2 Recess gate transistor 有权
标题翻译：凹槽门晶体管
公开(公告)号：US08012828B2
公开(公告)日：2011-09-06
申请号：US12251054
申请日：2008-10-14
申请人： Ji-Young Min , Si-Hyung Lee , Heedon Hwang , Si-Young Choi , Sangbom Kang , Dongsoo Woo
发明人： Ji-Young Min , Si-Hyung Lee , Heedon Hwang , Si-Young Choi , Sangbom Kang , Dongsoo Woo
IPC分类号： H01L21/336
CPC分类号： H01L29/66553 , H01L21/28079 , H01L21/28114 , H01L29/4236
摘要： A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.
摘要翻译：提供半导体器件的凹槽，其包括：形成有凹部的基板; 形成在所述凹部的底部的金属层; 形成在所述金属层上的多晶硅层; 以及与所述多晶硅层相邻形成并与所述金属层隔开形成的源极区域和漏极区域。还提供了一种形成半导体器件的方法，包括形成衬底和源极和漏极层; 形成凹部并在其中沉积栅极绝缘层; 在所述栅绝缘层上形成第一导电层; 通过使所述第一导电层凹陷来形成第一导电层图案; 在所述第一导电层图案上形成第二导电层; 通过图案化所述第二导电层以与所述源极和漏极层重叠而形成第二导电层图案; 在第二导电层图案和源极和漏极层上沉积绝缘层; 并且平坦化绝缘层以在第二导电层图案上形成帽。

3. 发明申请

US20090134448A1 Non-volatile memory device and method of forming the same 审中-公开
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20090134448A1
公开(公告)日：2009-05-28
申请号：US12230835
申请日：2008-09-05
申请人： Taek-Soo Jeon , Si-Young Choi , In-Sang Jeon , Sang-Bom Kang , Si-Hyung Lee , Seung-Hoon Hong
发明人： Taek-Soo Jeon , Si-Young Choi , In-Sang Jeon , Sang-Bom Kang , Si-Hyung Lee , Seung-Hoon Hong
IPC分类号： H01L29/68 , H01L21/336
CPC分类号： H01L29/4234 , H01L29/40117
摘要： Example embodiments provide a non-volatile semiconductor memory device and method of forming the same. The non-volatile memory device may include a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a first blocking insulation layer on the charge storage layer, and a gate electrode on the first blocking insulation layer, wherein the gate electrode includes aluminum and the first blocking insulation layer does not include aluminum.
摘要翻译：示例性实施例提供了一种非易失性半导体存储器件及其形成方法。非易失性存储器件可以包括半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的第一阻挡绝缘层和第一阻挡绝缘层上的栅电极，其中栅电极包括铝，并且第一阻挡绝缘层不包括铝。

4. 发明申请

US20080308876A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080308876A1
公开(公告)日：2008-12-18
申请号：US12155969
申请日：2008-06-12
申请人： Hye-Lan Lee , Si-Young Choi , Sang-Bom Kang , Si-Hyung Lee , Sang-Jin Hyun
发明人： Hye-Lan Lee , Si-Young Choi , Sang-Bom Kang , Si-Hyung Lee , Sang-Jin Hyun
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/4958 , H01L21/823828 , H01L27/092 , H01L29/4966
摘要： A semiconductor device includes a first gate structure on a first region of a substrate, the first gate structure including sequentially formed a first insulating layer pattern, a first conductive layer pattern, and a first polysilicon layer pattern doped with first impurities of a first conductivity type, a first source/drain in the first region of the substrate doped with second impurities of a second conductivity type, a second gate structure on a second region of the substrate, the second gate structure including sequentially formed a second insulating layer pattern, a second conductive layer pattern, and a second polysilicon layer pattern doped with third impurities with the first conductivity type, and a second source/drain in the second region of the substrate doped with fourth impurities having a conductivity type opposite the second conductivity.
摘要翻译：半导体器件包括在衬底的第一区域上的第一栅极结构，第一栅极结构包括顺序地形成第一绝缘层图案，第一导电层图案和掺杂有第一导电类型的第一杂质的第一多晶硅层图案掺杂有第二导电类型的第二杂质的衬底的第一区域中的第一源极/漏极，在衬底的第二区域上的第二栅极结构，第二栅极结构依次形成第二绝缘层图案，第二栅极结构导电层图案和掺杂有第一导电类型的第三杂质的第二多晶硅层图案，以及掺杂有具有与第二导电性相反的导电类型的第四杂质的第二基底的第二源极/漏极。

5. 发明授权

US08916460B1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08916460B1
公开(公告)日：2014-12-23
申请号：US14270315
申请日：2014-05-05
申请人： Byoung-Ho Kwon , Cheol Kim , Ho-Young Kim , Se-Jung Park , Myeong-Cheol Kim , Bo-Kyeong Kang , Bo-Un Yoon , Jae-Kwang Choi , Si-Young Choi , Suk-Hoon Jeong , Geum-Jung Seong , Hee-Don Jeong , Yong-Joon Choi , Ji-Eun Han
发明人： Byoung-Ho Kwon , Cheol Kim , Ho-Young Kim , Se-Jung Park , Myeong-Cheol Kim , Bo-Kyeong Kang , Bo-Un Yoon , Jae-Kwang Choi , Si-Young Choi , Suk-Hoon Jeong , Geum-Jung Seong , Hee-Don Jeong , Yong-Joon Choi , Ji-Eun Han
IPC分类号： H01L29/49 , H01L29/78 , H01L21/336 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7853 , H01L21/30604 , H01L21/3065 , H01L21/3085 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0673 , H01L29/42364 , H01L29/4238 , H01L29/49 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/78 , H01L29/785
摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
摘要翻译：半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。可以在第二绝缘体的顶表面上形成伪栅电极。还公开了其制造方法和修改方案。

6. 发明授权

US08546735B2 Microwave oven 有权
标题翻译：微波炉
公开(公告)号：US08546735B2
公开(公告)日：2013-10-01
申请号：US12744861
申请日：2008-11-20
申请人： Sung-Ho Choi , Kyu-Young Kim , Jae-Myung Chin , Sang-Ryul Lee , Dong-Han Kim , Si-Young Choi
发明人： Sung-Ho Choi , Kyu-Young Kim , Jae-Myung Chin , Sang-Ryul Lee , Dong-Han Kim , Si-Young Choi
IPC分类号： H05B6/64
CPC分类号： H05B6/642 , H05B6/6485
摘要： A microwave oven is provided. A barrier member prevents airflow provided by a fan assembly from being introduced again to the fan assembly. A separation member divides the airflow provided by the fan assembly to cool a first component and a second component. Thus, the components are efficiently cooled.
摘要翻译：提供微波炉。阻挡构件防止由风扇组件提供的气流再次被引入风扇组件。分离构件分隔由风扇组件提供的气流以冷却第一部件和第二部件。因此，组件被有效地冷却。

7. 发明授权

US08114735B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08114735B2
公开(公告)日：2012-02-14
申请号：US11902209
申请日：2007-09-20
申请人： Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Han-Mei Choi , Seung-Hwan Lee , Seung-Jae Baik , Sun-Jung Kim , Kwang-Min Park , In-Sun Yi
发明人： Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Han-Mei Choi , Seung-Hwan Lee , Seung-Jae Baik , Sun-Jung Kim , Kwang-Min Park , In-Sun Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28185 , H01L21/28194 , H01L21/28282 , H01L21/3185 , H01L29/4234 , H01L29/518 , H01L29/7923
摘要： In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.
摘要翻译：在制造非易失性存储器件的方法中，隧道绝缘层可以形成在衬底的沟道区上。可以在隧道绝缘层上形成包括氮化硅的电荷俘获层，以从沟道区捕获电子。可以使用包括氮气的第一气体和包括氧的第二气体来进行热处理，以去除电荷捕获层中的缺陷位点并致密化电荷捕获层。可以在热处理的电荷俘获层上形成阻挡层，然后可以在阻挡层上形成导电层。阻挡层，导电层，热处理电荷捕获层和隧道绝缘层可以被图案化以在沟道区上形成栅极结构。因此，可以提高包括门结构的非易失性存储器件的数据保持性能和/或可靠性。

8. 发明授权

US08039350B2 Methods of fabricating MOS transistors having recesses with elevated source/drain regions 有权
标题翻译：制造具有升高的源极/漏极区域的凹槽的MOS晶体管的方法
公开(公告)号：US08039350B2
公开(公告)日：2011-10-18
申请号：US12582073
申请日：2009-10-20
申请人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
发明人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.
摘要翻译：提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。凹陷区域设置在与栅极图案相邻的衬底中。外凹层设置在凹陷区域的底表面上。在外延层中设置高浓度杂质区。凹陷区域可以使用化学干蚀刻技术形成。

9. 发明申请

US20110147378A1 MICROWAVE OVEN 有权
标题翻译：微波炉
公开(公告)号：US20110147378A1
公开(公告)日：2011-06-23
申请号：US12935804
申请日：2009-04-01
申请人： Sang-Ryul Lee , Kyu-Young Kim , Jae-Myung Chin , Dong-Han Kim , Si-Young Choi , Sung-Ho Choi
发明人： Sang-Ryul Lee , Kyu-Young Kim , Jae-Myung Chin , Dong-Han Kim , Si-Young Choi , Sung-Ho Choi
IPC分类号： H05B6/64
CPC分类号： H05B6/708
摘要： A microwave oven includes a cavity having a cooking chamber; a magnetron oscillating microwave radiation used for cooking food in the cooking chamber; and a plurality of radiation openings through which the microwave radiation is radiated into the cooking chamber, each of the radiation openings having a length in a direction where the microwave radiation is guided by a waveguide, the length being greater or less than λ/4.
摘要翻译：微波炉包括具有烹饪室的空腔; 用于在烹饪室中烹饪食物的磁控管振荡微波辐射; 以及多个辐射开口，微波辐射通过该辐射开口辐射到烹饪室中，每个辐射开口具有在微波辐射被波导引导的方向上的长度，该长度大于或小于λ/ 4。

10. 发明申请

US20110114474A1 METHOD AND APPARATUS FOR DEPOSITION OF DIFFUSION THIN FILM 审中-公开
标题翻译：用于沉积薄膜沉积的方法和装置
公开(公告)号：US20110114474A1
公开(公告)日：2011-05-19
申请号：US12743706
申请日：2007-11-22
申请人： Sang-Youl Bae , Si-Young Choi , Sung-Youp Chung , Jung-Hyun Choi
发明人： Sang-Youl Bae , Si-Young Choi , Sung-Youp Chung , Jung-Hyun Choi
IPC分类号： C23C14/34 , C23C14/22 , C23C14/14 , C23C14/54
CPC分类号： C23C14/0641 , C23C14/325 , C23C14/345 , H01J37/34
摘要： This invention relates to a method and apparatus for deposition of a diffused thin film, useful in the fabrication of semiconductors and for the surface DC-Bias coating of various tools. In order to coat the surface of a treatment object, such as semiconductors, various molded products, or various tools, with a thin film, one or more process factors selected from among a bias voltage, a gas quantity, an arc power, and a sputtering power are continuously and variably adjusted, whereby the composition ratio of the thin film which is formed on the surface of the treatment object not through a chemical reaction but through a physical method is continuously varied, thus manufacturing a thin film having high hardness. The composition ratio of the thin film to be deposited is selected depending on the end use thereof, thereby depositing the thin film having superior wear resistance, impact resistance, and heat resistance.
摘要翻译：本发明涉及一种沉积扩散薄膜的方法和装置，可用于制造半导体和各种工具的表面直流偏置涂层。为了涂覆诸如半导体，各种模制产品或具有薄膜的各种工具的处理对象的表面，从偏置电压，气体量，电弧功率和溅射功率被连续且可变地调节，由此，不是通过化学反应而是通过物理方法形成在处理对象表面上的薄膜的组成比不断变化，因此制造具有高硬度的薄膜。要沉积的薄膜的组成比根据其最终用途来选择，从而沉积具有优异的耐磨性，耐冲击性和耐热性的薄膜。

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