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1. 发明申请

US20090134448A1 Non-volatile memory device and method of forming the same 审中-公开
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20090134448A1
公开(公告)日：2009-05-28
申请号：US12230835
申请日：2008-09-05
申请人： Taek-Soo Jeon , Si-Young Choi , In-Sang Jeon , Sang-Bom Kang , Si-Hyung Lee , Seung-Hoon Hong
发明人： Taek-Soo Jeon , Si-Young Choi , In-Sang Jeon , Sang-Bom Kang , Si-Hyung Lee , Seung-Hoon Hong
IPC分类号： H01L29/68 , H01L21/336
CPC分类号： H01L29/4234 , H01L29/40117
摘要： Example embodiments provide a non-volatile semiconductor memory device and method of forming the same. The non-volatile memory device may include a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a first blocking insulation layer on the charge storage layer, and a gate electrode on the first blocking insulation layer, wherein the gate electrode includes aluminum and the first blocking insulation layer does not include aluminum.
摘要翻译：示例性实施例提供了一种非易失性半导体存储器件及其形成方法。非易失性存储器件可以包括半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的第一阻挡绝缘层和第一阻挡绝缘层上的栅电极，其中栅电极包括铝，并且第一阻挡绝缘层不包括铝。

2. 发明申请

US20070032008A1 MOS semiconductor devices having polysilicon gate electrodes and high dielectric constant gate dielectric layers and methods of manufacturing such devices 审中-公开
标题翻译：具有多晶硅栅电极和高介电常数栅介电层的MOS半导体器件及其制造方法
公开(公告)号：US20070032008A1
公开(公告)日：2007-02-08
申请号：US11494100
申请日：2006-07-27
申请人： Hye-Min Kim , Yu-Gyun Shin , In-Sang Jeon , Sang-Bom Kang , Hong-Bae Park , Beom-Jun Jin
发明人： Hye-Min Kim , Yu-Gyun Shin , In-Sang Jeon , Sang-Bom Kang , Hong-Bae Park , Beom-Jun Jin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor device includes a substrate divided into an NMOS region and a PMOS region, a first gate pattern formed on the PMOS region, and a second gate pattern formed on the NMOS region. The first gate pattern includes a first gate oxide layer pattern, a metal oxide layer pattern, a silicon nitride layer pattern and a first polysilicon layer pattern that are sequentially stacked. The second gate pattern includes a second oxide layer pattern and a second polysilicon layer pattern. Related methods are also provided.
摘要翻译：半导体器件包括分为NMOS区和PMOS区的衬底，形成在PMOS区上的第一栅极图案，以及形成在NMOS区上的第二栅极图案。第一栅极图案包括依次层叠的第一栅极氧化物层图案，金属氧化物层图案，氮化硅层图案和第一多晶硅层图案。第二栅极图案包括第二氧化物层图案和第二多晶硅层图案。还提供了相关方法。

3. 发明申请

US20070063295A1 Gate electrode, method of forming the same, transistor having the gate electrode, method of manufacturing the same, semiconductor device having the gate electrode and method of manufacturing the same 审中-公开
标题翻译：栅电极，其形成方法，具有栅电极的晶体管，其制造方法，具有栅电极的半导体器件及其制造方法
公开(公告)号：US20070063295A1
公开(公告)日：2007-03-22
申请号：US11522343
申请日：2006-09-18
申请人： In-Sang Jeon , Yu-Gyun Shin , Sang-Bom Kang , Hong-Bae Park , Hye-Min Kim , Beom-Jun Jin
发明人： In-Sang Jeon , Yu-Gyun Shin , Sang-Bom Kang , Hong-Bae Park , Hye-Min Kim , Beom-Jun Jin
IPC分类号： H01L29/94
CPC分类号： H01L29/4983 , H01L21/28088 , H01L21/28194 , H01L21/823828 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/78
摘要： Example embodiments relate to a gate electrode, a method of forming the gate electrode, a transistor having the gate electrode, a method of manufacturing the transistor, a semiconductor device having the transistor and a method of manufacturing the semiconductor device. The gate electrode may include an embossing structure including a metal or a metal compound and having a first work function and a conductive layer pattern having a second work function formed on the embossing structure. A work function of the gate electrode may be adjusted between a work function of the embossing structure and a work function of the conductive layer pattern formed on the embossing structure. An NMOS transistor and a PMOS transistor having different work functions respectively may be formed on a substrate.
摘要翻译：示例性实施例涉及栅电极，形成栅电极的方法，具有栅电极的晶体管，制造晶体管的方法，具有晶体管的半导体器件和制造半导体器件的方法。栅电极可以包括包括金属或金属化合物并具有第一功函数的压花结构和在压花结构上形成的具有第二功函数的导电层图案。可以在压花结构的功函数和形成在压花结构上的导电层图案的功函数之间调整栅电极的功函数。可以在衬底上形成具有不同功函数的NMOS晶体管和PMOS晶体管。

4. 发明授权

US07692196B2 Memory devices and methods of manufacturing the same 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US07692196B2
公开(公告)日：2010-04-06
申请号：US11655689
申请日：2007-01-19
申请人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
发明人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
IPC分类号： H01L27/108
CPC分类号： H01L21/28282 , H01L29/513 , H01L29/792 , Y10S257/908
摘要： The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate. The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.
摘要翻译：存储器件包括在半导体衬底上的第一隧道绝缘层图案，第二隧道绝缘层图案，其第一隧道绝缘层图案上具有比第一隧道绝缘层图案低的能带隙，第二隧道绝缘层图案，电荷俘获层图案上的阻挡层图案，以及阻挡层图案上的栅电极。存储器件还包括在半导体衬底的上部的源极/漏极区域。半导体衬底的上部与第一隧道绝缘层图案相邻。

5. 发明申请

US20080164508A1 Memory devices and methods of manufacturing the same 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US20080164508A1
公开(公告)日：2008-07-10
申请号：US11655689
申请日：2007-01-19
申请人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
发明人： In-Sang Jeon , Sang-Bom Kang , Dong-Chan Kim , Chul-Sung Kim , Sug-Hun Hong , Sang-Jin Hyun
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L29/513 , H01L29/792 , Y10S257/908
摘要： The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate, The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.
摘要翻译：存储器件包括在半导体衬底上的第一隧道绝缘层图案，第二隧道绝缘层图案，其第一隧道绝缘层图案上具有比第一隧道绝缘层图案低的能带隙，第二隧道绝缘层图案，电荷俘获层图案上的阻挡层图案，以及阻挡层图案上的栅电极。存储器件还包括在半导体衬底的上部的源极/漏极区域。半导体衬底的上部与第一隧道绝缘层图案相邻。

6. 发明授权

US06348376B2 Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact and capacitor of semiconductor device using the same 有权
标题翻译：通过化学气相沉积形成金属氮化物膜的方法和使用其形成金属接触和半导体器件的电容器的方法
公开(公告)号：US06348376B2
公开(公告)日：2002-02-19
申请号：US09765531
申请日：2001-01-19
申请人： Hyun-Seok Lim , Sang-Bom Kang , In-Sang Jeon , Gil-Heyun Choi
发明人： Hyun-Seok Lim , Sang-Bom Kang , In-Sang Jeon , Gil-Heyun Choi
IPC分类号： H01L218242
CPC分类号： H01L21/76843 , C23C16/34 , C23C16/45553 , H01L21/28562 , H01L21/76804 , H01L28/91
摘要： A method of forming a metal nitride film using chemical vapor deposition (CVD), and a method of forming a metal contact and a semiconductor capacitor of a semiconductor device using the same, are provided. The method of forming a metal nitride film using chemical vapor deposition (CVD) in which a metal source and a nitrogen source are used as a precursor, includes the steps of inserting a semiconductor substrate into a deposition chamber, flowing the metal source into the deposition chamber, removing the metal source remaining in the deposition chamber by cutting off the inflow of the metal source and flowing a purge gas into the deposition chamber, cutting off the purge gas and flowing the nitrogen source into the deposition chamber to react with the metal source adsorbed on the semiconductor substrate, and removing the nitrogen source remaining in the deposition chamber by cutting off the inflow of the nitrogen source and flowing the purge gas into the deposition chamber. Accordingly, the metal nitride film having low resistivity and a low content of Cl even with excellent step coverage can be formed at a temperature of 500° C. or lower, and a semiconductor capacitor having excellent leakage current characteristics can be manufactured. Also, a deposition speed, approximately 20 A/cycle, is suitable for mass production.
摘要翻译：提供了使用化学气相沉积（CVD）形成金属氮化物膜的方法，以及使用其形成半导体器件的金属接触和半导体电容器的方法。使用其中使用金属源和氮源作为前体的化学气相沉积（CVD）形成金属氮化物膜的方法包括以下步骤：将半导体衬底插入淀积室中，使金属源流入沉积物通过切断金属源的流入并将净化气体流入沉积室，去除沉积室中残留的金属源，切断净化气体并使氮源流入沉积室以与金属源反应吸附在半导体衬底上，并且通过切断氮源的流入并将净化气体流入沉积室来除去留在沉积室中的氮源。因此，可以在500℃以下的温度下形成具有低电阻率和低Cl含量的金属氮化物膜，并且可以制造具有优异的漏电流特性的半导体电容器。此外，大约20A /周的沉积速度适合于批量生产。

7. 发明申请

US20100240180A1 Methods of Manufacturing Semiconductor Devices Having Low Resistance Buried Gate Structures 有权
标题翻译：制造具有低电阻掩埋栅极结构的半导体器件的方法
公开(公告)号：US20100240180A1
公开(公告)日：2010-09-23
申请号：US12725743
申请日：2010-03-17
申请人： In-Sang Jeon , Si-Hyung Lee , Jong-Ryeol Yoo , Yu-Gyun Shin , Suk-Hun Choi
发明人： In-Sang Jeon , Si-Hyung Lee , Jong-Ryeol Yoo , Yu-Gyun Shin , Suk-Hun Choi
IPC分类号： H01L21/336 , H01L21/8242
CPC分类号： H01L29/4236 , H01L21/67207 , H01L21/823437 , H01L21/823456 , H01L29/66621 , H01L29/78
摘要： In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.
摘要翻译：在制造半导体器件的方法中，在衬底的有源区中形成凹部。在第一凹部中形成栅极绝缘层。在栅绝缘层上形成阻挡层。在阻挡层上形成具有第一电阻的预成核层。将初始成核层转变成具有比第一电阻显着小的第二电阻的成核层。在成核层上形成导电层。所述导电层，所述成核层，阻挡层和该栅极绝缘层被部分地蚀刻，以形成包括栅极绝缘层图案，阻挡层图案，一个成核层图案和导电层图案的埋入栅极结构。

8. 发明授权

US08168521B2 Methods of manufacturing semiconductor devices having low resistance buried gate structures 有权
标题翻译：制造具有低电阻掩埋栅极结构的半导体器件的方法
公开(公告)号：US08168521B2
公开(公告)日：2012-05-01
申请号：US12725743
申请日：2010-03-17
申请人： In-Sang Jeon , Si-Hyung Lee , Jong-Ryeol Yoo , Yu-Ghun Shin , Suk-Hun Choi
发明人： In-Sang Jeon , Si-Hyung Lee , Jong-Ryeol Yoo , Yu-Ghun Shin , Suk-Hun Choi
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4236 , H01L21/67207 , H01L21/823437 , H01L21/823456 , H01L29/66621 , H01L29/78
摘要： In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.
摘要翻译：在制造半导体器件的方法中，在衬底的有源区中形成凹部。在第一凹部中形成栅极绝缘层。在栅绝缘层上形成阻挡层。在阻挡层上形成具有第一电阻的预成核层。将初始成核层转变成具有比第一电阻显着小的第二电阻的成核层。在成核层上形成导电层。部分蚀刻导电层，成核层，势垒层和栅极绝缘层，以形成包括栅极绝缘层图案，势垒层图案，成核层图案和导电层图案的掩埋栅极结构。

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