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1. 发明申请

US20070123697A1 Process for purifying interferon beta 有权
标题翻译：干扰素β的纯化方法
公开(公告)号：US20070123697A1
公开(公告)日：2007-05-31
申请号：US10581597
申请日：2004-12-04
申请人： Ji Sook Park , Jong Chung , Min Baek , Jee Ahn , Ki Kim , Hyung Park , Dong Lee , Myung Oh
发明人： Ji Sook Park , Jong Chung , Min Baek , Jee Ahn , Ki Kim , Hyung Park , Dong Lee , Myung Oh
IPC分类号： C07K14/56
CPC分类号： C07K14/565 , C12P21/02
摘要： Provided is a process for purifying human interferon beta from a recombinant human interferon beta-containing culture comprising performing affinity chromatography and cation exchange chromatography, wherein the affinity chromatography includes: adsorbing the interferon beta-containing culture to an equilibrated affinity chromatography column, followed by washing with an equilibration buffer solution; washing the column with a washing buffer solution A of pH 6.5-7.5 containing 30-60 wt % of propylene glycol and a washing buffer solution B of pH 6.5-7.5 containing 10-30 wt % of propylene glycol and 1-2M NaCl; and eluting a human interferon beta-containing fraction with a buffer solution of pH 6.5-7.5 containing 40-60 wt % of propylene glycol and 1-2M NaCl.
摘要翻译：提供了一种从重组人类干扰素β的培养物中纯化人类干扰素β的方法，包括进行亲和层析和阳离子交换层析，其中亲和层析包括：将含干扰素β的培养物吸附到平衡的亲和色谱柱上，然后洗涤用平衡缓冲溶液; 用含有30-60重量％丙二醇的pH 6.5-7.5的洗涤缓冲溶液A和pH6.5-7.5的洗涤缓冲液B洗涤柱子，其中含有10-30重量％的丙二醇和1-2M的NaCl; 并用含有40-60重量％丙二醇和1-2M NaCl的pH 6.5-7.5的缓冲溶液洗脱人类含有干扰素β的级分。

2. 发明申请

US20070093649A1 Process for purifying interferon beta 有权
标题翻译：干扰素β的纯化方法
公开(公告)号：US20070093649A1
公开(公告)日：2007-04-26
申请号：US10581602
申请日：2004-12-04
申请人： Ji Sook Park , Min Baek , Jee Ahn , Ki Kim , Hyung Park , Dong Lee , Myung Oh
发明人： Ji Sook Park , Min Baek , Jee Ahn , Ki Kim , Hyung Park , Dong Lee , Myung Oh
IPC分类号： C07K14/56
CPC分类号： C07K14/565 , C07K5/06139
摘要： Provided is a process for purifying human interferon beta from a recombinant human interferon beta-containing culture comprising performing affinity chromatography and reversed-phase high-performance liquid chromatography (RP-HPLC), wherein the affinity chromatography includes: adsorbing the interferon beta-containing culture to an equilibrated affinity chromatography column, followed by washing with an equilibration buffer solution; washing the column with a washing buffer solution A of pH 6.5-7.5 containing 30-60 wt % of propylene glycol and a washing buffer solution B of pH 6.5-7.5 containing 10-30 wt % of propylene glycol and 1-2M NaCl; and eluting a human interferon beta-containing fraction with a buffer solution of pH 6.5-7.5 containing 40-60 wt % of propylene glycol and 1-2M NaCl.
摘要翻译：提供了一种从重组人类干扰素β培养物中纯化人类干扰素β的方法，包括进行亲和层析和反相高效液相色谱（RP-HPLC），其中亲和层析包括：吸附含有干扰素β的培养物平衡的亲和层析柱，然后用平衡缓冲液洗涤; 用含有30-60重量％丙二醇的pH 6.5-7.5的洗涤缓冲溶液A和pH6.5-7.5的洗涤缓冲液B洗涤柱子，其中含有10-30重量％的丙二醇和1-2M的NaCl; 并用含有40-60重量％丙二醇和1-2M NaCl的pH 6.5-7.5的缓冲溶液洗脱人类含有干扰素β的级分。

3. 发明申请

US20050019871A1 Glycosylated human interferon alpha isoform 失效
标题翻译：糖基化人类干扰素α同种型
公开(公告)号：US20050019871A1
公开(公告)日：2005-01-27
申请号：US10653350
申请日：2003-09-02
申请人： Eun Jung Lee , Hyung Park , Hyun Seok Kim , Ji Sook Park , Yeon Hyang Kim , Hyune Soo Lee , Hyung Kon Koh , Myung Suk Oh
发明人： Eun Jung Lee , Hyung Park , Hyun Seok Kim , Ji Sook Park , Yeon Hyang Kim , Hyune Soo Lee , Hyung Kon Koh , Myung Suk Oh
IPC分类号： C07K14/56 , C12P21/02 , C07H21/04
CPC分类号： C07K14/56
摘要： The present invention relates to an amino acid-modified human interferon alpha isoform having at least one of the Asn-Xaa-Ser/Thr (N-X-S/T) sequence formed at a specific site so that glycosylation takes place at this site and a gene encoding the same, an expression vector comprising the gene, and a method for producing glycosylated human interferon alpha isoform by transforming or transfecting an eukaryotic cell with the expression vector, culturing the transfected or transformed cell and isolating the glycosylated human interferon alpha isoform from the culture, the glycosylated human interferon alpha isoform produced therefrom and a pharmaceutical composition comprising the same.
摘要翻译：本发明涉及具有在特定部位形成的至少一种Asn-Xaa-Ser / Thr（NXS / T）序列的氨基酸修饰的人类干扰素α同种型，使得在该位点发生糖基化，并编码基因相同的包含该基因的表达载体和通过用表达载体转化或转染真核细胞来产生糖基化的人干扰素α同种型的方法，培养转染或转化的细胞并从培养物中分离糖基化的人干扰素α同种型，由其制备的糖基化的人干扰素α同种型和包含其的药物组合物。

4. 发明申请

US20060033184A1 Process and lead frame for making leadless semiconductor packages 有权
标题翻译：用于制造无引线半导体封装的工艺和引线框架
公开(公告)号：US20060033184A1
公开(公告)日：2006-02-16
申请号：US10915326
申请日：2004-08-11
申请人： Hyung Park , Hyeong Kim , Sang Park , Yong Lee , Kyung Rho , Jun Yang , Jin Won
发明人： Hyung Park , Hyeong Kim , Sang Park , Yong Lee , Kyung Rho , Jun Yang , Jin Won
IPC分类号： H01L23/495
CPC分类号： H01L23/3107 , H01L21/561 , H01L21/568 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32245 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2224/85 , H01L2224/83 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. Each lead of the lead frame has a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion. After a wire bonding step and an encapsulating step are conducted, a second metal layer is selectively plated on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product. Then, the third portion of each lead is selectively etched away such that the first portion and the second portion are electrically isolated from each other. Finally, a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.
摘要翻译：公开了一种用于制造多个无引线封装的工艺。首先，将芯片附着在其上形成有第一金属层的引线框架上。引线框架的每个引线具有连接第一部分和第二部分的第一部分，第二部分和第三部分，其中第一金属层未设置在第三部分上。在进行引线接合步骤和封装步骤之后，选择性地将第二金属层电镀在引线的第一部分和第二部分以及从模制产品的底部露出的芯片焊盘。然后，选择性地蚀刻每个引线的第三部分，使得第一部分和第二部分彼此电隔离。最后，进行一个单独的步骤来完成这个过程。本发明还提供了一种新的引线框设计。

5. 发明申请

US20050148186A1 Slurry composition with high planarity and CMP process of dielectric film using the same 失效
标题翻译：具有高平坦度的浆料组合物和使用其的介电膜的CMP工艺
公开(公告)号：US20050148186A1
公开(公告)日：2005-07-07
申请号：US10999263
申请日：2004-11-30
申请人： Jong Jung , Sang Lee , Hyung Park
发明人： Jong Jung , Sang Lee , Hyung Park
IPC分类号： H01L21/304 , C09G1/02 , H01L21/3105 , H01L21/768 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76819 , C09G1/02 , H01L21/31053
摘要： Disclosed herein are a CMP slurry composition with high-planarity and a CMP process for polishing a dielectric film using the same. More specifically, a CMP slurry composition with high-planarity includes a carbon compound having tens of thousands of carboxyl groups and having a molecular weight ranging from hundreds of thousands to millions, an abrasive, and water. A CMP process for polishing a dielectric film utilizes the disclosed slurry composition. The slurry composition enables complete and overall planarization of the dielectric film by polishing the part of the film having a higher step difference through CMP process. Accordingly, the disclosed slurry composition is useful for the CMP process of all semiconductor devices including those having ultrafine patterns.
摘要翻译：本文公开了具有高平面性的CMP浆料组合物和使用其的用于抛光电介质膜的CMP工艺。更具体地说，具有高平面度的CMP浆料组合物包括具有数万个羧基并且分子量范围从数十万到数百万的碳化合物，研磨剂和水。用于抛光电介质膜的CMP工艺利用所公开的浆料组合物。浆料组合物通过CMP工艺研磨具有较高阶梯差的薄膜的部分，能够使电介质薄膜完全和全面平坦化。因此，所公开的浆料组合物对于包括具有超细图案的半导体器件的所有半导体器件的CMP工艺是有用的。

6. 发明申请

US20050142867A1 Method for forming polysilicon plug of semiconductor device 有权
标题翻译：用于形成半导体器件的多晶硅插塞的方法
公开(公告)号：US20050142867A1
公开(公告)日：2005-06-30
申请号：US10879220
申请日：2004-06-30
申请人： Hyung Park , Min Lee , Sang Lee , Hyun Sohn
发明人： Hyung Park , Min Lee , Sang Lee , Hyun Sohn
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/7684
摘要： Disclosed is a method for forming a polysilicon plug of a semiconductor device. The method comprises the steps of: forming a stacked pattern of a wordline and a hard mask film on a semiconductor substrate comprising a cell region and a peripheral circuit region; forming a spacer on a sidewall of the stacked pattern; forming an interlayer insulating film on the semiconductor substrate; polishing the interlayer insulating film via a CMP process using the hard mask film as a polishing barrier film; forming a barrier film on the semiconductor substrate including the interlayer insulating film; selectively etching the barrier film and the interlayer insulating film to form a landing plug contact hole; depositing a polysilicon film filling the landing plug contact hole on the semiconductor substrate; blanket-etching the polysilicon film using the barrier film as an etching barrier film; and polishing the polysilicon film and the barrier film using the hard mask film as a polishing barrier film to form a polysilicon plug.
摘要翻译：公开了一种用于形成半导体器件的多晶硅插塞的方法。该方法包括以下步骤：在包括单元区域和外围电路区域的半导体衬底上形成字线和硬掩模膜的堆叠图案; 在所述堆叠图案的侧壁上形成间隔物; 在半导体衬底上形成层间绝缘膜; 通过使用硬掩模膜作为抛光阻挡膜的CMP工艺来研磨层间绝缘膜; 在包括层间绝缘膜的半导体衬底上形成阻挡膜; 选择性地蚀刻阻挡膜和层间绝缘膜以形成着陆塞接触孔; 在所述半导体衬底上沉积填充所述着地插头接触孔的多晶硅膜; 使用阻挡膜作为蚀刻阻挡膜对多晶硅膜进行绝缘蚀刻; 并使用硬掩模膜作为抛光阻挡膜研磨多晶硅膜和阻挡膜以形成多晶硅插塞。

7. 发明申请

US20050095834A1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050095834A1
公开(公告)日：2005-05-05
申请号：US10875052
申请日：2004-06-22
申请人： Sang Lee , Jong Shin , Hyung Park
发明人： Sang Lee , Jong Shin , Hyung Park
IPC分类号： H01L21/283 , H01L21/304 , H01L21/44 , H01L21/4763 , H01L21/60 , H01L21/768 , H01L21/822 , H01L21/8242
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10855 , H01L27/10873 , H01L27/10888
摘要： Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first BPSG layer on a resultant structure of the substrate, performing a first CVD process for the first BPSG layer, forming a second BPSG layer on the first BPSG layer, forming a landing plug contact, depositing a polysilicon layer on a resultant structure of the substrate, and performing a second CMP process for the polysilicon layer, the second BPSG layer and the nitride hard mask. The CMP processes are carried by using acid slurry having a high polishing selectivity with respect to the nitride layer, so a step difference between the cell region and the peripheral region is removed, thereby simplifying the semiconductor manufacturing process and removing a dishing phenomenon.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：在衬底上形成栅极，在衬底的表面上形成接合区域，在衬底的所得结构上形成第一BPSG层，对第一BPSG层执行第一CVD工艺，形成第二BPSG 在第一BPSG层上形成着色插头接触，在所得衬底的所得结构上沉积多晶硅层，以及对多晶硅层，第二BPSG层和氮化物硬掩模执行第二CMP工艺。通过使用相对于氮化物层具有高抛光选择性的酸性浆料来进行CMP处理，从而消除了单元区域和外围区域之间的阶跃差异，从而简化了半导体制造工艺并消除了凹陷现象。

8. 发明申请

US20070157790A1 Locking tailpiece 有权
标题翻译：锁定尾巴
公开(公告)号：US20070157790A1
公开(公告)日：2007-07-12
申请号：US11330712
申请日：2006-01-12
申请人： Dong Kim , Hyung Park , James Rosenberg , Richard Akers
发明人： Dong Kim , Hyung Park , James Rosenberg , Richard Akers
IPC分类号： G10D3/04
CPC分类号： G10D3/04
摘要： Included herein is an instrument component for mounting to the body of an instrument having strings, for example a guitar. The instrument component comprises a plurality of attachment devices, an elongated bracket, and a biasing element. The elongated bracket includes a plurality of attachment apertures where each aperture includes a center and is shaped to accept one of the attachment devices. A biasing element is positioned in each attachment aperture wherein each biasing element engages one of the attachment devices. Each biasing element includes a plurality of protrusions wherein each protrusion biases the attachment device toward the center of the attachment aperture.
摘要翻译：这里包括用于安装到具有弦的乐器的身体的乐器部件，例如吉他。仪器部件包括多个附接装置，细长支架和偏置元件。细长支架包括多个附接孔，其中每个孔包括一个中心并成形为接受一个连接装置。偏置元件定位在每个附接孔中，其中每个偏置元件接合附接装置中的一个。每个偏置元件包括多个突起，其中每个突出部朝着连接孔的中心偏压附接装置。

9. 发明申请

US20070130951A1 Combustor 审中-公开
标题翻译：燃烧器
公开(公告)号：US20070130951A1
公开(公告)日：2007-06-14
申请号：US11377685
申请日：2006-03-17
申请人： Hae Choi , Hyung Park , Woo Jeon
发明人： Hae Choi , Hyung Park , Woo Jeon
IPC分类号： F23R3/42
CPC分类号： F23R3/44 , F23D11/406 , F23D14/70 , F23R3/18 , F23R3/42
摘要： Provided is a combustor comprising an entrance through which the fuel flows thereinto; a combustion chamber, connected to the entrance, having a larger cross-section area than that of the entrance; and a plurality of protrusions installed along the interface of the entrance and the combustion chamber. Thus, the combustor according to the present invention has an enhanced mixing capability of fuel and air in the combustion chamber, thereby having enhanced combustion efficiency and reduced discharge of harmful exhaust gas.
摘要翻译：提供了一种燃烧器，其包括燃料流过其中的入口; 连接到入口的燃烧室具有比入口大的横截面面积; 以及沿着入口和燃烧室的界面安装的多个突起。因此，根据本发明的燃烧器具有燃烧室中燃料和空气的混合能力增强，从而具有提高的燃烧效率和减少排放有害废气。

10. 发明申请

US20070102715A1 Semiconductor light emitting device 失效
标题翻译：半导体发光器件
公开(公告)号：US20070102715A1
公开(公告)日：2007-05-10
申请号：US11588330
申请日：2006-10-27
申请人： Kun Ko , Young Park , Bok Min , Hyung Park , Seok Hwang
发明人： Kun Ko , Young Park , Bok Min , Hyung Park , Seok Hwang
IPC分类号： H01L33/00
CPC分类号： H01L33/20 , H01L33/14 , H01L33/32
摘要： The invention relates to a high-quality semiconductor light emitting device which suppresses current concentration. The semiconductor light emitting device includes an n-type semiconductor layer, an active layer and a p-type semiconductor layer sequentially formed on a substrate. The semiconductor light emitting device further includes a p-electrode formed on the p-type semiconductor layer and an n-electrode formed on a surface of a mesa-etched portion of the n-type semiconductor layer. A trench is formed in the n-type semiconductor layer to prevent current concentration. The trench is extended from an upper surface of the mesa-etched portion of the n-type semiconductor layer or from a bottom surface of the substrate into the n-type semiconductor layer at a predetermined depth.
摘要翻译：本发明涉及抑制电流浓度的高质量半导体发光器件。半导体发光器件包括依次形成在衬底上的n型半导体层，有源层和p型半导体层。半导体发光器件还包括形成在p型半导体层上的p电极和形成在n型半导体层的台面蚀刻部分的表面上的n电极。在n型半导体层中形成沟槽以防止电流集中。沟槽从n型半导体层的台面蚀刻部分的上表面或从基板的底表面延伸到预定深度的n型半导体层。

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