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1. 发明授权

US07167181B2 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US07167181B2
公开(公告)日：2007-01-23
申请号：US10458493
申请日：2003-06-09
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1/20 , G06T15/40 , G09G5/00
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺的帧缓冲器和多个阶段隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

2. 发明授权

US07164426B1 Method and apparatus for generating texture 有权
标题翻译：用于产生纹理的方法和装置
公开(公告)号：US07164426B1
公开(公告)日：2007-01-16
申请号：US09724663
申请日：2000-11-28
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Joseph P. Grass , Abbas Rashid , Bo Hong , Abraham Mammen
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Joseph P. Grass , Abbas Rashid , Bo Hong , Abraham Mammen
IPC分类号： G06F12/00 , G06F12/02 , G06T11/40
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.
摘要翻译：一种延迟图形流水线处理器，包括与纹理单元相关联的纹理单元和纹理存储器。纹理单元将存储在纹理存储器中的纹理映射应用于像素片段。纹理是MIP映射的，并且包括不同细节级别的一系列纹理贴图，每个贴图表示在距离眼点的给定距离处的纹理的外观。纹理单元从纹理图执行三线性插值，以产生近似正确的细节水平的给定像素片段的纹理值。纹理存储器以减少存储器访问冲突的方式存储和访问纹理数据，从而提高所述纹理单元的吞吐量。

3. 发明授权

US06288730B1 Method and apparatus for generating texture 有权
标题翻译：用于产生纹理的方法和装置
公开(公告)号：US06288730B1
公开(公告)日：2001-09-11
申请号：US09378408
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Joseph P. Grass , Abbas Rashid , Bo Hong , Abraham Mammen
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Joseph P. Grass , Abbas Rashid , Bo Hong , Abraham Mammen
IPC分类号： G06T1140
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.
摘要翻译：一种延迟图形流水线处理器，包括与纹理单元相关联的纹理单元和纹理存储器。纹理单元将存储在纹理存储器中的纹理映射应用于像素片段。纹理是MIP映射的，并且包括不同细节级别的一系列纹理贴图，每个贴图表示在距离眼点的给定距离处的纹理的外观。纹理单元从纹理图执行三线性插值，以产生近似正确的细节水平的给定像素片段的纹理值。纹理存储器以减少存储器访问冲突的方式存储和访问纹理数据，从而提高所述纹理单元的吞吐量。

4. 发明授权

US07808503B2 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US07808503B2
公开(公告)日：2010-10-05
申请号：US11613093
申请日：2006-12-19
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Yo , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Yo , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1/20 , G06T15/00 , G06T15/10
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

5. 发明授权

US06717576B1 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US06717576B1
公开(公告)日：2004-04-06
申请号：US09377503
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1500
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

6. 发明授权

US08495111B1 System and method of hierarchical space management for storage systems 有权
标题翻译：存储系统分级空间管理系统和方法
公开(公告)号：US08495111B1
公开(公告)日：2013-07-23
申请号：US12236194
申请日：2008-09-23
申请人： Feng Wang , John A. Colgrove , Bo Hong , Oleg Kiselev
发明人： Feng Wang , John A. Colgrove , Bo Hong , Oleg Kiselev
IPC分类号： G06F17/30
CPC分类号： G06F3/0604 , G06F3/0619 , G06F3/0631 , G06F3/0644 , G06F3/0683 , G06F11/0727 , G06F11/0793
摘要： A system and method for storing data. In one embodiment, a storage system includes a resource manager and a hierarchical entry tree describing storage entities of the storage system. At each given level of the tree higher than the bottom level, metadata entries summarize storage availability at a level below the given level. The resource manager receives a request to store data of a target size at a target location corresponding to a first portion of the entry tree and scans the entry tree to determine if contiguous, free storage entities of the target size are available at the target location. In response to determining that contiguous, free storage entities of the target size are not available at the target location, the resource manager scans portions of the entry tree outside the first portion to identify contiguous, free storage entities of the target size, where it stores the data.
摘要翻译：一种用于存储数据的系统和方法。在一个实施例中，存储系统包括描述存储系统的存储实体的资源管理器和分层条目树。在高于底层的树的每个给定级别，元数据条目将存储可用性总结在低于给定级别的级别。资源管理器接收在对应于条目树的第一部分的目标位置处存储目标大小的数据的请求，并扫描条目树，以确定目标大小的连续的空闲存储实体是否在目标位置可用。响应于确定目标大小的连续的空闲存储实体在目标位置不可用，资源管理器扫描第一部分之外的条目树的部分，以识别目标大小的连续的空闲存储实体，其中存储数据。

7. 发明授权

US08468318B2 Scheduling of I/O writes in a storage environment 有权
公开(公告)号：US08468318B2
公开(公告)日：2013-06-18
申请号：US12882877
申请日：2010-09-15
申请人： John Colgrove , John Hayes , Bo Hong , Feng Wang , Ethan Miller , Craig Harmer
发明人： John Colgrove , John Hayes , Bo Hong , Feng Wang , Ethan Miller , Craig Harmer
IPC分类号： G06F12/00
CPC分类号： G06F3/0611 , G06F3/06 , G06F3/061 , G06F3/0613 , G06F3/0629 , G06F3/0653 , G06F3/0655 , G06F3/0656 , G06F3/0659 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F12/0238 , G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/0891 , G06F2003/0697 , G06F2212/60
摘要： A system and method for scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency.

8. 发明申请

US20120079190A1 OFFSET PROTECTION DATA IN A RAID ARRAY 有权
标题翻译： RAID阵列中的偏移保护数据
公开(公告)号：US20120079190A1
公开(公告)日：2012-03-29
申请号：US12892895
申请日：2010-09-28
申请人： John Colgrove , John Hayes , Bo Hong , Ethan Miller
发明人： John Colgrove , John Hayes , Bo Hong , Ethan Miller
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F11/1076 , G06F3/0605 , G06F3/0688 , G06F11/3034 , G06F11/3055 , G06F2211/1057 , G06F2211/1059
摘要： A system and method for offset protection data in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to store user data in a first page of a first storage device of the plurality of storage devices; generate intra-device protection data corresponding to the user data, and store the intra-device protection data at a first offset within the first page. The controller is further configured to generate inter-device protection data corresponding to the first page, and store the inter-device protection data at a second offset within a second page in a second storage device of the plurality of storage devices, wherein the first offset is different from the second offset.
摘要翻译： RAID阵列中偏移保护数据的系统和方法。计算机系统包括经由网络彼此耦合的客户端计算机和数据存储阵列。数据存储阵列利用固态驱动器和闪存单元进行数据存储。数据存储阵列中的存储控制器被配置为将用户数据存储在多个存储设备中的第一存储设备的第一页中; 生成对应于用户数据的设备内保护数据，并将设备内保护数据存储在第一页内的第一偏移处。所述控制器还被配置为产生对应于所述第一页的设备间保护数据，并且将所述设备间保护数据存储在所述多个存储设备中的第二存储设备中的第二页内的第二偏移处，其中所述第一偏移与第二偏移不同。

9. 发明申请

US20120066448A1 SCHEDULING OF REACTIVE I/O OPERATIONS IN A STORAGE ENVIRONMENT 有权
标题翻译：在存储环境中调度反应性I / O操作
公开(公告)号：US20120066448A1
公开(公告)日：2012-03-15
申请号：US12882864
申请日：2010-09-15
申请人： John Colgrove , John Hayes , Bo Hong , Feng Wang , Ethan Miller , Craig Harmer
发明人： John Colgrove , John Hayes , Bo Hong , Feng Wang , Ethan Miller , Craig Harmer
IPC分类号： G06F12/00
CPC分类号： G06F3/0611 , G06F3/061 , G06F3/0613 , G06F3/0617 , G06F3/0634 , G06F3/0659 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F11/0751 , G06F11/076 , G06F11/1076
摘要： A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The characteristics of corresponding storage devices are used to schedule I/O requests to the storage devices in order to maintain relatively consistent response times at predicted times. Should a device exhibit an unscheduled behavior which may be indicative of the device being in an unknown state, the scheduler may schedule one or more reactive operations on the device configured to cause the device to enter a known state.
摘要翻译：一种用于在多个固态存储设备之间有效地调度读取和写入操作的系统和方法。计算机系统包括经由网络彼此耦合的客户端计算机和数据存储阵列。数据存储阵列利用固态驱动器和闪存单元进行数据存储。数据存储阵列中的存储控制器包括I / O调度器。相应的存储设备的特性用于将I / O请求调度到存储设备，以便在预测时间内保持相对一致的响应时间。如果设备呈现可能指示设备处于未知状态的非计划行为，则调度器可以对被配置为使设备进入已知状态的设备上的一个或多个无效操作进行调度。

10. 发明申请

US20100118043A1 RECONFIGURABLE HIGH-PERFORMANCE TEXTURE PIPELINE WITH ADVANCED FILTERING 有权
标题翻译：可重复使用的高性能纹路管道，具有先进的过滤功能
公开(公告)号：US20100118043A1
公开(公告)日：2010-05-13
申请号：US12689939
申请日：2010-01-19
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J.M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J.M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
IPC分类号： G09G5/00
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。

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