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1. 发明授权

US08749568B2 Parameter FIFO 有权
公开(公告)号：US08749568B2
公开(公告)日：2014-06-10
申请号：US12685166
申请日：2010-01-11
申请人： Joseph P. Bratt , Shing Choo , Peter F. Holland , Timothy J. Millet
发明人： Joseph P. Bratt , Shing Choo , Peter F. Holland , Timothy J. Millet
IPC分类号： G09G5/36
CPC分类号： G06T1/60 , G09G5/14 , G09G5/363 , G09G2340/10 , G09G2360/12 , G09G2360/127
摘要： A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

2. 发明授权

US08749565B2 Error check-only mode 有权
标题翻译：错误检查模式
公开(公告)号：US08749565B2
公开(公告)日：2014-06-10
申请号：US12950239
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland , David L. Bowman
发明人： Joseph P. Bratt , Peter F. Holland , David L. Bowman
IPC分类号： G06T1/60
CPC分类号： G09G5/397 , G09G5/36 , G09G2330/12 , G09G2340/0407 , G09G2340/06 , G09G2340/10 , G09G2340/125 , G09G2360/10 , G09G2360/125
摘要： Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available. The results generated by the error-checking may be read and compared to an expected value to detect test pass/fail conditions.
摘要翻译：视频显示管道可以用FIFO（先进先出）缓冲器终止，从而将像素提供给显示控制器以在图形/视频显示器上显示像素。显示管道可以以比显示控制器从FIFO缓冲器提取像素的速率高得多的速率来频繁地处理像素。在仅错误检查模式中，FIFO可以被禁用，并且连接在FIFO前面的错误校验（例如CRC）块可以像显示管能够处理显示管一样快地接收由显示管处理的像素像素。因此，执行测试所需的测试/模拟时间的长度可以由生成像素的速率而不是显示控制器显示像素的速率来确定。在不支持显示或不可用的环境中也可以进行测试/模拟。可以读取错误检查产生的结果并将其与期望值进行比较，以检测测试通过/失败条件。

3. 发明授权

US08711170B2 Edge alphas for image translation 有权
标题翻译：边缘图像翻译
公开(公告)号：US08711170B2
公开(公告)日：2014-04-29
申请号：US13026559
申请日：2011-02-14
申请人： Joseph P. Bratt , Peter F. Holland , Gokhan Avkarogullari
发明人： Joseph P. Bratt , Peter F. Holland , Gokhan Avkarogullari
IPC分类号： G09G5/02
CPC分类号： G06T15/005 , G06T13/80 , G06T15/503
摘要： A video display pipe used for processing pixels of video and/or image frames may include edge Alpha registers for storing edge Alpha values corresponding to the edges of an image to be translated across a display screen. The edge Alpha values may be specified based on the fractional pixel value by which the image is to be moved in the current frame. The video pipe may copy the column and row of pixels that are in the direction of travel, and may apply the edge Alpha values to the copied column and row. The edge Alpha values may control blending of the additional column and row of the translated image with the adjacent pixels in the original frame, providing the effect of the partial pixel movement, simulating a sub-pixel rate of movement.
摘要翻译：用于处理视频和/或图像帧的像素的视频显示管可以包括边缘Alpha寄存器，用于存储与通过显示屏幕翻译的图像的边缘相对应的边缘α值。可以基于在当前帧中移动图像的分数像素值来指定边缘Alpha值。视频管道可以复制行进方向的像素列和行，并且可以将边缘Alpha值应用于复制的列和行。边缘Alpha值可以控制翻转图像的附加列和行与原始帧中的相邻像素的混合，从而提供部分像素移动的效果，模拟子像素移动速率。

4. 发明授权

US08493482B2 Dual image sensor image processing system and method 有权
标题翻译：双图像传感器图像处理系统及方法
公开(公告)号：US08493482B2
公开(公告)日：2013-07-23
申请号：US12858922
申请日：2010-08-18
申请人： Guy Cote , Jeffrey E. Frederiksen , Joseph P. Bratt , Shun Wai Go , Timothy J. Millet
发明人： Guy Cote , Jeffrey E. Frederiksen , Joseph P. Bratt , Shun Wai Go , Timothy J. Millet
IPC分类号： H04N3/14 , H04N5/335 , H01L31/062
CPC分类号： H04N5/232 , H04N5/2258 , H04N5/23245
摘要： Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.
摘要翻译：提供了用于处理使用数字图像传感器获取的图像数据的各种技术。根据本公开的方面，一种这样的技术可以涉及在支持多个图像传感器的系统中对图像数据的处理。在一个实施例中，图像处理系统可以包括被配置为确定设备是以单个传感器模式（一个有源传感器）或双传感器模式（两个有源传感器）操作的控制电路。当在单传感器模式下操作时，数据可以从有源传感器的传感器接口直接提供给前端像素处理单元。当以双传感器模式操作时，来自第一和第二传感器的图像帧以交错的方式提供给前端像素处理单元。例如，在一个实施例中，来自第一和第二传感器的图像帧被写入存储器，然后以交错的方式读出到前端像素处理单元。

5. 发明申请

US20120206657A1 Reproducible Dither-noise Injection 有权
标题翻译：可重现的抖动噪声注入
公开(公告)号：US20120206657A1
公开(公告)日：2012-08-16
申请号：US13026557
申请日：2011-02-14
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
IPC分类号： H04N9/64
CPC分类号： H04N9/646 , G06F7/584 , G09G2320/0271
摘要： A display pipe unit for processing pixels of video and/or image frames may be injected with dither-noise during processing of the pixels. A random noise generator implemented using Linear Feedback Shift Registers (LFSRs) produces pseudo-random numbers that are injected into the display pipe as dither-noise. Typically, such LFSRs shift freely during operation and the values of the LFSRs are used as needed. By shifting the LFSRs when the values are used to inject noise into newly received data, and not shifting the LFSRs when no new data is received, variations in the delays of receiving the data do not affect the pattern of noise applied to the frames. Therefore, dither-noise can be deterministically injected into the display pipe during testing/debug operation. By updating the LFSRs when new pixel data is available from the host interface instead of updating the LFSRs every cycle, the same dither-noise can be injected for the same received data.
摘要翻译：用于处理视频和/或图像帧的像素的显示管单元可以在处理像素期间被注入抖动噪声。使用线性反馈移位寄存器（LFSR）实现的随机噪声发生器产生作为抖动噪声注入显示管道的伪随机数。通常，这样的LFSR在操作期间自由移动，并且根据需要使用LFSR的值。当使用这些值将噪声注入到新接收到的数据中时，通过移位LFSR，并且在没有接收到新数据时不移动LFSR，接收数据的延迟的变化不影响施加到帧的噪声模式。因此，在测试/调试操作期间，可以将抖动噪声确定性地注入显示管道。当从主机接口获得新像素数据而不是每个周期更新LFSR时，通过更新LFSR，可以为相同的接收数据注入相同的抖动噪声。

6. 发明申请

US20120206468A1 Edge Alphas for Image Translation 有权
标题翻译：边缘阿尔法图像翻译
公开(公告)号：US20120206468A1
公开(公告)日：2012-08-16
申请号：US13026559
申请日：2011-02-14
申请人： Joseph P. Bratt , Peter F. Holland , Gokhan Avkarogullari
发明人： Joseph P. Bratt , Peter F. Holland , Gokhan Avkarogullari
IPC分类号： G09G5/36
CPC分类号： G06T15/005 , G06T13/80 , G06T15/503
摘要： A video display pipe used for processing pixels of video and/or image frames may include edge Alpha registers for storing edge Alpha values corresponding to the edges of an image to be translated across a display screen. The edge Alpha values may be specified based on the fractional pixel value by which the image is to be moved in the current frame. The video pipe may copy the column and row of pixels that are in the direction of travel, and may apply the edge Alpha values to the copied column and row. The edge Alpha values may control blending of the additional column and row of the translated image with the adjacent pixels in the original frame, providing the effect of the partial pixel movement, simulating a sub-pixel rate of movement.
摘要翻译：用于处理视频和/或图像帧的像素的视频显示管可以包括边缘Alpha寄存器，用于存储与通过显示屏幕翻译的图像的边缘相对应的边缘α值。可以基于在当前帧中移动图像的分数像素值来指定边缘Alpha值。视频管道可以复制行进方向的像素列和行，并且可以将边缘Alpha值应用于复制的列和行。边缘Alpha值可以控制翻转图像的附加列和行与原始帧中的相邻像素的混合，从而提供部分像素移动的效果，模拟子像素移动速率。

7. 发明申请

US20120044372A1 DUAL IMAGE SENSOR IMAGE PROCESSING SYSTEM AND METHOD 有权
标题翻译：双图像传感器图像处理系统和方法
公开(公告)号：US20120044372A1
公开(公告)日：2012-02-23
申请号：US12858922
申请日：2010-08-18
申请人： Guy Côté , Jeffrey E. Frederiksen , Joseph P. Bratt , Shun Wai Go , Timothy J. Millet
发明人： Guy Côté , Jeffrey E. Frederiksen , Joseph P. Bratt , Shun Wai Go , Timothy J. Millet
IPC分类号： H04N5/225 , H04N5/228
CPC分类号： H04N5/232 , H04N5/2258 , H04N5/23245
摘要： Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.
摘要翻译：提供了用于处理使用数字图像传感器获取的图像数据的各种技术。根据本公开的方面，一种这样的技术可以涉及在支持多个图像传感器的系统中对图像数据的处理。在一个实施例中，图像处理系统可以包括被配置为确定设备是以单个传感器模式（一个有源传感器）或双传感器模式（两个有源传感器）操作的控制电路。当在单传感器模式下操作时，数据可以从有源传感器的传感器接口直接提供给前端像素处理单元。当以双传感器模式操作时，来自第一和第二传感器的图像帧以交错的方式提供给前端像素处理单元。例如，在一个实施例中，来自第一和第二传感器的图像帧被写入存储器，然后以交错的方式读出到前端像素处理单元。

8. 发明授权

US07984317B2 Hardware-based power management of functional blocks 有权
标题翻译：功能块的基于硬件的电源管理
公开(公告)号：US07984317B2
公开(公告)日：2011-07-19
申请号：US12053807
申请日：2008-03-24
申请人： David G. Conroy , Timothy J. Millet , Joseph P. Bratt
发明人： David G. Conroy , Timothy J. Millet , Joseph P. Bratt
IPC分类号： G06F1/28
CPC分类号： G06F1/30 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for setting the local power state of the functional block. For each power control domain in the implementation, hardware uses these local power states and sets the actual operating state of the power control domain accordingly.
摘要翻译：公开了一种用于在便携式电子设备中使用的各种功能块之间有效管理功率分配的系统和方法。该方法包括允许每个功能块被独立控制，包含其自己的低级软件和用于设置功能块的本地功率状态的功率控制。对于实现中的每个功率控制域，硬件使用这些本地电源状态，并相应地设置功率控制域的实际工作状态。

9. 发明申请

US20090240959A1 BLOCK BASED POWER MANAGEMENT 有权
标题翻译：基于块的电源管理
公开(公告)号：US20090240959A1
公开(公告)日：2009-09-24
申请号：US12053807
申请日：2008-03-24
申请人： David G. Conroy , Timothy J. Millet , Joseph P. Bratt
发明人： David G. Conroy , Timothy J. Millet , Joseph P. Bratt
IPC分类号： G06F1/00
CPC分类号： G06F1/30 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for setting the local power state of the functional block. For each power control domain in the implementation, hardware uses these local power states and sets the actual operating state of the power control domain accordingly.
摘要翻译：公开了一种用于在便携式电子设备中使用的各种功能块之间有效管理功率分配的系统和方法。该方法包括允许每个功能块被独立控制，包含其自己的低级软件和用于设置功能块的本地功率状态的功率控制。对于实现中的每个功率控制域，硬件使用这些本地电源状态，并相应地设置功率控制域的实际工作状态。

10. 发明授权

US07558947B1 Method and apparatus for computing vector absolute differences 有权
标题翻译：用于计算矢量绝对差的方法和装置
公开(公告)号：US07558947B1
公开(公告)日：2009-07-07
申请号：US10038431
申请日：2001-12-31
申请人： Sushma Shrikant Trivedi , Joseph P. Bratt , Vaughn Todd Arnold , William C. Athas , Jason Chen
发明人： Sushma Shrikant Trivedi , Joseph P. Bratt , Vaughn Todd Arnold , William C. Athas , Jason Chen
IPC分类号： G06F7/38
CPC分类号： G06F7/544 , G06F2207/5442
摘要： Methods and apparatuses for computing an absolute difference of two vectors of numbers. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a first plurality of numbers and a second plurality of numbers; and generating simultaneously a third plurality of numbers, each of which is an absolute difference between a number in the first plurality of numbers and a number in the second plurality of numbers. The above operations are performed in response to the microprocessor receiving the single instruction.
摘要翻译：用于计算两个数字向量的绝对差的方法和装置。在本发明的一个方面中，微处理器响应于接收单个指令而执行的方法包括：接收第一多个数字和第二多个数字; 并且同时产生第三多个数字，每个数字是第一多个数字中的数字和第二个多个数字中的数字之间的绝对差。响应于微处理器接收到单个指令执行上述操作。

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