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1. 发明授权

US06514844B1 Sidewall treatment for low dielectric constant (low K) materials by ion implantation 失效
标题翻译：通过离子注入对低介电常数（低K）材料进行侧壁处理
公开(公告)号：US06514844B1
公开(公告)日：2003-02-04
申请号：US09840598
申请日：2001-04-23
申请人： Jeremy I. Martin , Eric M. Apelgren , Christian Zistl , Paul R. Besser , Srikantewara Dakshina-Murthy , Jonathan B. Smith , Nick Kepler , Fred Cheung
发明人： Jeremy I. Martin , Eric M. Apelgren , Christian Zistl , Paul R. Besser , Srikantewara Dakshina-Murthy , Jonathan B. Smith , Nick Kepler , Fred Cheung
IPC分类号： H01L2144
CPC分类号： H01L21/76825 , H01L21/31155 , H01L21/76801 , H01L21/76807 , H01L21/7681 , H01L21/76877
摘要： A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.
摘要翻译：提供了一种方法，该方法包括形成第一导电结构，以及在第一导电结构之上形成第一电介质层。该方法还包括在第一导电结构的至少一部分上方致密化第一电介质层的一部分，以及在第一介电层的致密部分中形成第一开口。

2. 发明授权

US06406993B1 Method of defining small openings in dielectric layers 有权
标题翻译：定义介电层中小开口的方法
公开(公告)号：US06406993B1
公开(公告)日：2002-06-18
申请号：US09523439
申请日：2000-03-10
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/76831
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括形成电介质材料层，在介电材料层之上形成硬掩模层，并在硬掩模层中形成开口。所述方法还包括在所述硬掩模层中的所述开口中形成侧壁间隔物，所述开口限定缩小的开口，在所述还原开口下方的介电材料层中形成开口，以及在所述电介质层的所述开口中形成导电互连。

3. 发明授权

US06610594B2 Locally increasing sidewall density by ion implantation 有权
公开(公告)号：US06610594B2
公开(公告)日：2003-08-26
申请号：US09902024
申请日：2001-07-10
申请人： Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Paul R. Besser , Fred Cheung
发明人： Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Paul R. Besser , Fred Cheung
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/31155 , H01L21/76802 , H01L21/7681 , H01L21/76828 , H01L21/76834 , H01L2924/0002 , H01L2924/00
摘要： A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.

4. 发明授权

US07737021B1 Resist trim process to define small openings in dielectric layers 有权
标题翻译：抵抗修整过程以限定电介质层中的小开口
公开(公告)号：US07737021B1
公开(公告)日：2010-06-15
申请号：US10261613
申请日：2002-09-30
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括在形成在电介质材料层上方的光致抗蚀剂层中限定具有第一尺寸的光致抗蚀剂特征。该方法还包括减小光致抗蚀剂特征的第一尺寸以产生减小尺寸的光致抗蚀剂特征，在减小尺寸的光致抗蚀剂特征下的电介质材料层中形成开口，以及在电介质材料层中的开口中形成导电材料。

5. 发明授权

US06500755B2 Resist trim process to define small openings in dielectric layers 有权
标题翻译：抵抗修整过程以限定电介质层中的小开口
公开(公告)号：US06500755B2
公开(公告)日：2002-12-31
申请号：US09731577
申请日：2000-12-06
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括在形成在电介质材料层上方的光致抗蚀剂层中限定具有第一尺寸的光致抗蚀剂特征。该方法还包括减小光致抗蚀剂特征的第一尺寸以产生减小尺寸的光致抗蚀剂特征，在减小尺寸的光致抗蚀剂特征下的电介质材料层中形成开口，以及在电介质材料层中的开口中形成导电材料。

6. 发明授权

US06294472B1 Dual slurry particle sizes for reducing microscratching of wafers 有权
标题翻译：用于减少晶片显微镜的双重浆料粒径
公开(公告)号：US06294472B1
公开(公告)日：2001-09-25
申请号：US09576750
申请日：2000-05-23
申请人： Jonathan B. Smith , Paul R. Besser , Jeremy I. Martin
发明人： Jonathan B. Smith , Paul R. Besser , Jeremy I. Martin
IPC分类号： H01L2100
CPC分类号： C09G1/02 , B24B37/044 , B24B57/02 , H01L21/30625
摘要： A method includes providing at least one wafer having a process layer formed thereon for polishing. The process layer is polished using a first polishing process that is associated with a slurry having a first abrasive particle size. The process layer is polished using a second polishing process that is associated with a slurry having a second abrasive particle size that is different from the first abrasive particle size. A system includes a polishing tool and a process controller. The polishing tool is adapted to receive at least one wafer having a process layer formed thereon for polishing. The polishing tool is adapted to polish the process layer using a first polishing process that is associated with a slurry having a first abrasive particle size. The polishing tool is adapted to polish the process layer using a second polishing process that is associated with a slurry having a second abrasive particle size that is different from the first abrasive particle size. The process controller is coupled to the polishing tool and adapted to communicate with at least one of a slurry controller and the polishing tool.
摘要翻译：一种方法包括提供至少一个晶片，其上形成有用于抛光的工艺层。使用与具有第一研磨粒度的浆料相关联的第一抛光工艺来抛光工艺层。使用与具有不同于第一磨料颗粒尺寸的第二磨料颗粒尺寸的浆料相关联的第二抛光方法来抛光工艺层。系统包括抛光工具和过程控制器。抛光工具适于接收至少一个晶片，其上形成有用于抛光的工艺层。抛光工具适于使用与具有第一研磨粒度的浆料相关联的第一抛光工艺来抛光工艺层。抛光工具适于使用与具有不同于第一磨料颗粒尺寸的第二磨料颗粒尺寸的浆料相关联的第二抛光工艺来抛光工艺层。过程控制器耦合到抛光工具并且适于与浆料控制器和抛光工具中的至少一个连通。

7. 发明授权

US06989601B1 Copper damascene with low-k capping layer and improved electromigration reliability 有权
标题翻译：具有低k覆盖层的铜镶嵌和改善的电迁移可靠性
公开(公告)号：US06989601B1
公开(公告)日：2006-01-24
申请号：US10946071
申请日：2004-09-22
申请人： Minh van Ngo , Jeremy I. Martin , Hartmut Ruelke
发明人： Minh van Ngo , Jeremy I. Martin , Hartmut Ruelke
IPC分类号： H01L23/48
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76826 , H01L21/76834 , H01L21/76883 , Y10S438/931
摘要： The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH3 diluted with N2, discontinuing the plasma and flow of NH3 and N2, pumping out the chamber; introducing trimethylsilane, NH3 and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 Å to about 800 Å. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.
摘要翻译：通过在其上沉积低k覆盖层，例如具有约4.5至约5.5的介电常数的碳化硅覆盖层，Cu线的电迁移电阻显着提高。实施方案包括用包含用N 2 N 2稀释的NH 3的等离子体依次处理镶嵌的Cu的暴露的平坦化表面，停止等离子体和NH 3的流动 >和N 2 2，泵出室; 引入三甲基硅烷NH 3和He，引发PECVD以沉积碳化硅覆盖层，厚度为约至约800。实施例还包括形成在介电常数（k）小于约3.9的电介质材料中的Cu双镶嵌结构。

8. 发明授权

US06797652B1 Copper damascene with low-k capping layer and improved electromigration reliability 失效
标题翻译：具有低k覆盖层的铜镶嵌和改善的电迁移可靠性
公开(公告)号：US06797652B1
公开(公告)日：2004-09-28
申请号：US10097965
申请日：2002-03-15
申请人： Minh van Ngo , Jeremy I. Martin , Hartmut Ruelke
发明人： Minh van Ngo , Jeremy I. Martin , Hartmut Ruelke
IPC分类号： H01L2100
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76826 , H01L21/76834 , H01L21/76883 , Y10S438/931
摘要： The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH3 diluted with N2, discontinuing the plasma and flow of NH3 and N2, pumping out the chamber; introducing trimethylsilane, NH3 and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 Å to about 800 Å. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.
摘要翻译：通过在其上沉积低k覆盖层，例如具有约4.5至约5.5的介电常数的碳化硅覆盖层，Cu线的电迁移电阻显着提高。实施方案包括用包含用N 2稀释的NH 3的等离子体依次处理嵌入的Cu的平坦化表面，停止等离子体和NH 3和N 2的流动，泵出室; 引入三甲基硅烷，NH 3和He，引发PECVD以沉积碳化硅覆盖层，厚度为约至约800。实施例还包括形成在介电常数（k）小于约3.9的电介质材料中的Cu双镶嵌结构。

9. 发明授权

US06600333B1 Method and test structure for characterizing sidewall damage in a semiconductor device 失效
标题翻译：用于表征半导体器件中侧壁损伤的方法和测试结构
公开(公告)号：US06600333B1
公开(公告)日：2003-07-29
申请号：US09501958
申请日：2000-02-10
申请人： Jeremy I. Martin , Nicholas J. Kepler , Larry L. Zhao
发明人： Jeremy I. Martin , Nicholas J. Kepler , Larry L. Zhao
IPC分类号： G01R2726
CPC分类号： H01L22/34 , G01R31/2884
摘要： A test circuit includes a wafer, an insulative layer formed on the wafer, and a plurality of test structures formed in the insulative layer. Each of the test structures comprises a first comb having a first plurality of fingers and a second comb having a second plurality of fingers. The first and second pluralities of fingers are interleaved to define a finger spacing between the first and second pluralities of fingers. The finger spacing in a first one of the test structures being different than the finger spacing in a second one of the test structures. A method for characterizing damage in a semiconductor device includes providing a wafer having an insulative layer and a plurality of test structures formed in the insulative layer. The test structures have different geometries. An electrical characteristic of first and second test structures of the plurality of test structures is determined. The electrical characteristics of the first and second test structures is compared. Damage to the insulative layer is characterized based on the comparison.
摘要翻译：测试电路包括晶片，形成在晶片上的绝缘层，以及形成在绝缘层中的多个测试结构。每个测试结构包括具有第一多个指状物的第一梳子和具有第二多个指状物的第二梳子。手指的第一和第二多个交织以限定第一和第二多个手指之间的手指间隔。测试结构中第一个测试结构中的手指间距不同于第二个测试结构中的手指间距。用于表征半导体器件中的损伤的方法包括提供具有绝缘层的晶片和形成在绝缘层中的多个测试结构。测试结构具有不同的几何形状。确定多个测试结构的第一和第二测试结构的电特性。比较第一和第二测试结构的电气特性。基于比较，对绝缘层的损伤进行了表征。

10. 发明授权

US06498112B1 Graded oxide caps on low dielectric constant (low K) chemical vapor deposition (CVD) films 有权
标题翻译：低介电常数（低K）化学气相沉积（CVD）膜上的分级氧化物盖
公开(公告)号：US06498112B1
公开(公告)日：2002-12-24
申请号：US09904943
申请日：2001-07-13
申请人： Jeremy I. Martin , Ting Yiu Tsui
发明人： Jeremy I. Martin , Ting Yiu Tsui
IPC分类号： H01L2131
CPC分类号： C23C16/45523 , H01L21/02126 , H01L21/02274 , H01L21/02362 , H01L21/31612 , H01L21/31633 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/7684 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method is provided, the method comprising forming a first dielectric layer above a structure layer, the first dielectric layer having an upper portion. The method also comprises grading the upper portion of the first dielectric layer using at least one of monomethyl silane, dimethyl silane, trimethyl silane, and tetramethyl silane with helium (He) and at least one of nitrous oxide (N2O) and molecular nitrogen (O2).
摘要翻译：提供了一种方法，所述方法包括在结构层上形成第一介电层，所述第一介电层具有上部。该方法还包括使用单甲基硅烷，二甲基硅烷，三甲基硅烷和四甲基硅烷中的至少一种与氦（He）和至少一种一氧化二氮（N 2 O）和分子氮（O 2）中的至少一种来分级第一介电层的上部）。

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