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1. 发明授权

US5888861A Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow 失效
标题翻译：制造完全集成在CMOS工艺流程中的BiCMOS集成电路的方法
公开(公告)号：US5888861A
公开(公告)日：1999-03-30
申请号：US870474
申请日：1997-06-06
申请人： Chung-Jen Chien , Jeong Y. Choi , Chuen-Der Lien
发明人： Chung-Jen Chien , Jeong Y. Choi , Chuen-Der Lien
IPC分类号： H01L21/8249 , H01L21/8238
CPC分类号： H01L21/8249
摘要： A process for manufacturing a BiCMOS integrated circuit is implemented by adapting the masking and doping steps used in forming CMOS devices. Thus simultaneous formation of both CMOS and bipolar device structures eliminates the need for any additional masking or process steps to form bipolar device structures. Collector regions 20 of NPN transistors are formed simultaneously with N-wells 18. Collector regions of PNP transistors, if required, are formed simultaneously with P-wells 16. Base regions 24 of the bipolar transistors are formed using threshold voltage implant steps and/or lightly doped drain implant steps of PMOS transistors. Emitter regions 59 are formed, when using a single polysilicon CMOS process, simultaneously with the CMOS gates 72, 74. When employing a double polysilicon CMOS process, the emitter regions 59 are formed concurrently with the second polysilicon layer interconnect structure and/or source/drain regions 50,52 of NMOS transistors. For single polysilicon CMOS process, the buried layer regions 66 are formed during buried contact formation.
摘要翻译： BiCMOS集成电路的制造工艺通过适应用于形成CMOS器件的掩模和掺杂步骤来实现。因此同时形成CMOS和双极器件结构消除了对形成双极器件结构的任何附加掩模或工艺步骤的需要。 NPN晶体管的集电极区域20与N阱18同时形成。如果需要，PNP晶体管的集电极区域与P阱16同时形成。双极晶体管的基极区域24使用阈值电压注入步骤和/或 PMOS晶体管的轻掺杂漏极注入步骤。当使用单个多晶硅CMOS工艺时，发射极区59与CMOS栅极72,74同时形成。当采用双重多晶硅CMOS工艺时，发射极区59与第二多晶硅层互连结构和/或源/ NMOS晶体管的漏极区域50,52。对于单多晶硅CMOS工艺，在掩埋接触形成期间形成掩埋层区域66。

2. 发明授权

US5128731A Static random access memory cell using a P/N-MOS transistors 失效
标题翻译：使用P / N-MOS晶体管的静态随机存取存储单元
公开(公告)号：US5128731A
公开(公告)日：1992-07-07
申请号：US537848
申请日：1990-06-13
申请人： Chuen-Der Lien , Fu-Chieh Hsu , Jeong Y. Choi , Jeng-Jiun Yang
发明人： Chuen-Der Lien , Fu-Chieh Hsu , Jeong Y. Choi , Jeng-Jiun Yang
IPC分类号： H01L27/11
CPC分类号： H01L27/1104
摘要： A P/N-MOS transistor having source and drain of opposite semiconductor types is provided. One embodiment of the P/N-MOS transistor has turn-off characteristic similar to a PMOS transistor, and turn-on characteristic similar to a PMOS transistor connected in series with a p-n junction diode. An application of the P/N-MOS transistor is provided in a static random access memory (SRAM) cell. This SRAM cell has density advantage over SRAM cells using polysilicon PMOS transistors as active transistors.
摘要翻译：提供了具有相反半导体类型的源极和漏极的P / N-MOS晶体管。 P / N-MOS晶体管的一个实施例具有类似于PMOS晶体管的截止特性，以及类似于与p-n结二极管串联连接的PMOS晶体管的导通特性。在静态随机存取存储器（SRAM）单元中提供了P / N-MOS晶体管的应用。该SRAM单元相对于使用多晶硅PMOS晶体管作为有源晶体管的SRAM单元具有密度优势。

3. 发明授权

US06191460B1 Identical gate conductivity type static random access memory cell 有权
标题翻译：相同的栅极导电型静态随机存取存储单元
公开(公告)号：US06191460B1
公开(公告)日：2001-02-20
申请号：US09390454
申请日：1999-09-07
申请人： Jeong Y. Choi , Chuen-Der Lien
发明人： Jeong Y. Choi , Chuen-Der Lien
IPC分类号： H02L2994
CPC分类号： H01L27/11 , H01L27/1104
摘要： A static random access memory cell is given increased stability and latch-up immunity by using N-type gate NMOS transistors and P-type gate PMOS transistors in the control and sensing circuits, but using the same gate conductivity type for both the NMOS and PMOS memory cell transistors. For example, both NMOS and PMOS memory cell transistors have N-type gates. Weakening the memory cell load transistors by lightly doping the source and/or drain regions further enhances stability.
摘要翻译：通过在控制和感测电路中使用N型栅极NMOS晶体管和P型栅极PMOS晶体管，给静态随机存取存储器单元提供了更高的稳定性和闭锁抑制能力，但对NMOS和PMOS使用相同的栅极导电类型存储单元晶体管。例如，NMOS和PMOS存储单元晶体管都具有N型栅极。通过轻掺杂源极和/或漏极区来减弱存储器单元负载晶体管进一步增强了稳定性。

4. 发明授权

US5926704A Efficient method for fabricating P-wells and N-wells 失效
标题翻译：用于制造P井和N井的有效方法
公开(公告)号：US5926704A
公开(公告)日：1999-07-20
申请号：US879558
申请日：1997-06-20
申请人： Jeong Y. Choi , Chuen-Der Lien
发明人： Jeong Y. Choi , Chuen-Der Lien
IPC分类号： H01L21/762 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/76218 , H01L21/823892 , H01L27/0928
摘要： A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in successive steps the field regions of the P- and N-wells; (ii) creating an oxide layer over the field regions, (iii) creating in successive steps the active regions. The method achieves the P- and N-wells without increasing the number of photoresist masking steps. In addition, optical alignment targets (OATs) are optionally formed simultaneously with these P- and N-wells without increasing the total number of process steps.
摘要翻译：一种方法在CMOS半导体衬底中形成具有独立优化的场区域和有源区域的P-阱和N阱。在一个实施方案中，通过以下步骤形成P-阱和N阱：（i）在连续步骤中产生P-阱和N阱的场区; （ii）在场区域上产生氧化物层，（iii）在连续步骤中产生活性区域。该方法在不增加光致抗蚀剂掩模步骤的数量的情况下实现P-阱和N阱。此外，光学取向靶（OAT）任选地与这些P-孔和N-孔同时形成，而不增加工艺步骤的总数。

5. 发明授权

US5679588A Method for fabricating P-wells and N-wells having optimized field and active regions 失效
标题翻译：具有优化场和活性区的P阱和N阱的方法
公开(公告)号：US5679588A
公开(公告)日：1997-10-21
申请号：US539801
申请日：1995-10-05
申请人： Jeong Y. Choi , Chuen-Der Lien
发明人： Jeong Y. Choi , Chuen-Der Lien
IPC分类号： H01L21/762 , H01L21/8238 , H01L27/092 , H01L21/265
CPC分类号： H01L21/76218 , H01L21/823892 , H01L27/0928
摘要： A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in successive steps the field regions of the P- and N-wells; (ii) creating an oxide layer over the field regions, (iii) creating in successive steps the active regions. The method achieves the P- and N-wells without increasing the number of photoresist masking steps. In addition, optical alignment targets (OATs) are optionally formed simultaneously with these P- and N-wells without increasing the total number of process steps.
摘要翻译：一种方法在CMOS半导体衬底中形成具有独立优化的场区域和有源区域的P-阱和N阱。在一个实施方案中，通过以下步骤形成P阱和N阱：（i）在连续步骤中产生P-阱和N阱的场区; （ii）在场区域上产生氧化物层，（iii）在连续步骤中产生活性区域。该方法在不增加光致抗蚀剂掩模步骤的数量的情况下实现P-阱和N阱。此外，光学取向靶（OAT）任选地与这些P-孔和N-孔同时形成，而不增加工艺步骤的总数。

6. 发明授权

US5393677A Method of optimizing wells for PMOS and bipolar to yield an improved BICMOS process 失效
标题翻译：优化PMOS和双极的阱以产生改进的BICMOS工艺的方法
公开(公告)号：US5393677A
公开(公告)日：1995-02-28
申请号：US20234
申请日：1993-02-19
申请人： Chuen-Der Lien , Kyle W. Terrill , Jeong Y. Choi
发明人： Chuen-Der Lien , Kyle W. Terrill , Jeong Y. Choi
IPC分类号： H01L21/8249 , H01L21/265
CPC分类号： H01L21/8249
摘要： A first process embodiment of the present invention comprises the steps of implanting a blanket low dose n-well implant before field oxidation. A blanket n-type punchthrough suppression implant precedes the field oxidation step. After field oxidation, an implantation masking step is used to adjust the doping for the p-well in its active and field regions.
摘要翻译：本发明的第一种方法实施方案包括在场氧化之前植入覆盖低剂量的n阱植入物的步骤。在场氧化步骤之前，一个覆盖的n型穿通抑制植入物。在场氧化之后，使用注入掩模步骤来调整其活性区域和场区中p阱的掺杂。

7. 发明授权

US07941723B1 Clock generator and method for providing reliable clock signal using array of MEMS resonators 有权
标题翻译：时钟发生器和使用MEMS谐振器阵列提供可靠时钟信号的方法
公开(公告)号：US07941723B1
公开(公告)日：2011-05-10
申请号：US11861869
申请日：2007-09-26
申请人： Chuen-Der Lien , Jimmy Lee
发明人： Chuen-Der Lien , Jimmy Lee
IPC分类号： G01R31/3181 , G01R31/40
CPC分类号： G01R31/31702 , G01R31/31727 , H03B5/32
摘要： A clock generator is disclosed that includes an array of MEMS resonators and a test circuit. The test circuit is operable at start-up to operate one or more of the MEMS resonators to generate test output and analyze the test output to determine whether the operated MEMS resonators meet test criteria. A MEMS resonator is selected that meets the test criteria and its output is used to generate an output clock signal. In addition, the test circuit is operable to analyze the output of the selected MEMS resonator and select a replacement MEMS resonator when the output of the selected MEMS resonator no longer meets the test criteria. The replacement MEMS resonator is then operated and its output is coupled to the output of the clock generator. Thereby, failing and potentially failing MEMS resonators are automatically replaced during operation of the clock generator in its end-use application.
摘要翻译：公开了一种包括MEMS谐振器阵列和测试电路的时钟发生器。测试电路在启动时可操作以操作一个或多个MEMS谐振器以产生测试输出并分析测试输出以确定所操作的MEMS谐振器是否符合测试标准。选择符合测试标准的MEMS谐振器，并且其输出用于产生输出时钟信号。另外，当选择的MEMS谐振器的输出不再满足测试标准时，测试电路可操作以分析所选择的MEMS谐振器的输出并选择替换的MEMS谐振器。然后更换MEMS谐振器，并将其输出耦合到时钟发生器的输出端。因此，在其最终用途应用中的时钟发生器的操作期间，故障和潜在故障的MEMS谐振器被自动替换。

8. 发明授权

US07522438B1 Method and apparatus for CAM with reduced cross-coupling interference 有权
公开(公告)号：US07522438B1
公开(公告)日：2009-04-21
申请号：US11931573
申请日：2007-10-31
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/02
摘要： A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.

9. 发明授权

US07187571B1 Method and apparatus for CAM with reduced cross-coupling interference 有权
标题翻译：具有降低的交叉耦合干扰的CAM的方法和装置
公开(公告)号：US07187571B1
公开(公告)日：2007-03-06
申请号：US10821601
申请日：2004-04-09
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00 , G11C7/00
CPC分类号： G11C15/04 , G11C7/02
摘要： A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.
摘要翻译：已经公开了一种具有减小的交叉耦合干扰的CAM的方法和装置。

10. 发明授权

US06879504B1 Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same 有权
标题翻译：具有错误检测和校正控制电路的内容可寻址存储器（CAM）装置及其操作方法
公开(公告)号：US06879504B1
公开(公告)日：2005-04-12
申请号：US10619638
申请日：2003-07-15
申请人： Chuen-Der Lien , Kee Park , Chau-Chin Wu , Mark Baumann
发明人： Chuen-Der Lien , Kee Park , Chau-Chin Wu , Mark Baumann
IPC分类号： G11C7/02 , G11C11/412 , G11C15/04 , G11C15/00
CPC分类号： G11C15/04 , G11C11/4125 , G11C15/043 , G11C15/046
摘要： Content addressable memory (CAM) devices include error detection and correction (EDC) control circuits therein. The EDC control circuit operates to correct soft errors in entries within a plurality of internal CAM array blocks with, at most, limited interruption to other operations performed by the CAM device. The EDC control circuit utilizes a multi-bit check word associated with each entry to detect a soft error and perform one-bit error correction on the entry. The EDC control circuit is configured to be active during a background mode of operation when the CAM array blocks are undergoing search operations in a foreground mode of operation. A CAM array block may also include a column of dual-function check bit cells that are configured to operate as a column of CAM cells when necessary to replace a defective column of CAM cells.
摘要翻译：内容可寻址存储器（CAM）装置包括其中的错误检测和校正（EDC）控制电路。 EDC控制电路用于校正多个内部CAM阵列块内的条目中的软错误，最多限制中断由CAM设备执行的其他操作。 EDC控制电路利用与每个条目相关联的多位检查字来检测软错误，并在条目上执行一位错误校正。当CAM阵列块在前台操作模式下正在进行搜索操作时，EDC控制电路被配置为在后台操作模式期间有效。 CAM阵列块还可以包括一列双功能校验位单元，其被配置为当需要更换CAM单元的缺陷列时作为CAM单元的列进行操作。

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