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1. 发明授权

US07033945B2 Gap filling with a composite layer 失效
标题翻译：间隙填充复合层
公开(公告)号：US07033945B2
公开(公告)日：2006-04-25
申请号：US10857829
申请日：2004-06-01
申请人： Jeong Soo Byun , Zheng Yuan , Shankar Venkataraman , M. Ziaul Karim , Thanh N. Pham , Ellie Y. Yieh
发明人： Jeong Soo Byun , Zheng Yuan , Shankar Venkataraman , M. Ziaul Karim , Thanh N. Pham , Ellie Y. Yieh
IPC分类号： H01L21/311
CPC分类号： H01L21/76224
摘要： A method of filling a gap formed between adjacent raised surfaces on a substrate. In one embodiment the method comprises depositing a boron-doped silica glass (BSG) layer over the substrate to partially fill the gap using a thermal CVD process; exposing the BSG layer to a steam ambient at a temperature above the BSG layer's Eutectic temperature; removing an upper portion of the BSG layer by exposing the layer to a fluorine-containing etchant; and depositing an undoped silica glass (USG) layer over the BSG layer to fill the remainder of the gap.
摘要翻译：填充在基板上相邻的凸起表面之间形成的间隙的方法。在一个实施例中，该方法包括在衬底上沉积硼掺杂石英玻璃（BSG）层，以使用热CVD工艺部分填充间隙; 在高于BSG层的共晶温度的温度下将BSG层暴露于蒸汽环境; 通过将层暴露于含氟蚀刻剂来除去BSG层的上部; 以及在BSG层上沉积未掺杂的二氧化硅玻璃（USG）层以填补间隙的剩余部分。

2. 发明授权

US07528051B2 Method of inducing stresses in the channel region of a transistor 失效
标题翻译：在晶体管的沟道区域中产生应力的方法
公开(公告)号：US07528051B2
公开(公告)日：2009-05-05
申请号：US10846734
申请日：2004-05-14
申请人： Reza Arghavani , Zheng Yuan , Ellie Y. Yieh , Shankar Venkataraman , Nitin K. Ingle
发明人： Reza Arghavani , Zheng Yuan , Ellie Y. Yieh , Shankar Venkataraman , Nitin K. Ingle
IPC分类号： H01L21/76
CPC分类号： H01L29/6656 , H01L21/823807 , H01L29/6659 , H01L29/7833 , H01L29/7846
摘要： A method of fabricating a semiconductor device, where the method includes forming a transistor on a substrate, where the transistor includes a channel region configured to conduct charge between a source region and a drain region, forming a trench adjacent to the transistor, depositing a material on the substrate and within the trench, and annealing the material, where the material is tensile following the annealing and creates a tensile stress in the channel region. Also, a method of forming a trench isolation in a semiconductor device, where the method includes forming a trench in a substrate, forming a material within the trench at a lower deposition rate, forming the material on the substrate at a higher deposition rate after the depositing of the material within the trench, and annealing the material, where after the annealing the material in the trench is tensile.
摘要翻译：一种制造半导体器件的方法，其中所述方法包括在衬底上形成晶体管，其中所述晶体管包括被配置为在源极区域和漏极区域之间传导电荷的沟道区域，形成与所述晶体管相邻的沟槽，在衬底上和沟槽内，并对材料进行退火，其中材料在退火之后是拉伸的，并且在沟道区域中产生拉伸应力。另外，在半导体器件中形成沟槽隔离的方法，其中所述方法包括在衬底中形成沟槽，以较低的沉积速率在沟槽内形成材料，在衬底上以更高的沉积速率在衬底上形成材料在沟槽内沉积材料并退火材料，其中在退火之后，沟槽中的材料是拉伸的。

3. 发明授权

US08153348B2 Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch 有权
标题翻译：用于形成图案化硬掩模膜（RFP）的工艺顺序，无需光致抗蚀剂或干蚀刻
公开(公告)号：US08153348B2
公开(公告)日：2012-04-10
申请号：US12034000
申请日：2008-02-20
申请人： Srinivas D. Nemani , Shankar Venkataraman , Ellie Y. Yieh
发明人： Srinivas D. Nemani , Shankar Venkataraman , Ellie Y. Yieh
IPC分类号： G03F7/26
CPC分类号： G03F7/0757 , H01L21/02164 , H01L21/3086 , H01L21/3105 , H01L21/31111 , H01L21/31612 , H01L21/6719 , H01L21/67207
摘要： Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.
摘要翻译：根据本发明的一个实施方案公开了使用紫外光图案化硬掩膜的方法和系统。本发明的实施例减轻了沉积和蚀刻光刻胶的处理问题，以产生硬掩模图案。首先将诸如氧化硅的硬掩模层沉积在沉积室内的衬底上。在一些情况下，硬掩模层在沉积之后被烘烤或退火。之后，硬掩模层的一部分用紫外线照射。紫外光产生硬掩模材料的暴露和未曝光部分的图案。曝光后，可能会发生腐蚀过程，例如湿蚀刻，从而去除硬掩模的未曝光部分。在蚀刻之后，可以对硬掩模进行退火，烘烤或进行等离子体处理。

4. 发明申请

US20090208880A1 PROCESS SEQUENCE FOR FORMATION OF PATTERNED HARD MASK FILM (RFP) WITHOUT NEED FOR PHOTORESIST OR DRY ETCH 有权
标题翻译：用于形成图形硬片（RFP）的过程序列，不需要用于光刻胶或干蚀刻
公开(公告)号：US20090208880A1
公开(公告)日：2009-08-20
申请号：US12034000
申请日：2008-02-20
申请人： SRINIVAS D. NEMANI , Shankar Venkataraman , Ellie Y. Yieh
发明人： SRINIVAS D. NEMANI , Shankar Venkataraman , Ellie Y. Yieh
IPC分类号： G03F7/00 , C23F1/00
CPC分类号： G03F7/0757 , H01L21/02164 , H01L21/3086 , H01L21/3105 , H01L21/31111 , H01L21/31612 , H01L21/6719 , H01L21/67207
摘要： Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.
摘要翻译：根据本发明的一个实施方案公开了使用紫外光图案化硬掩膜的方法和系统。本发明的实施例减轻了沉积和蚀刻光刻胶的处理问题，以产生硬掩模图案。首先将诸如氧化硅的硬掩模层沉积在沉积室内的衬底上。在一些情况下，硬掩模层在沉积之后被烘烤或退火。之后，硬掩模层的一部分用紫外线照射。紫外光产生硬掩模材料的暴露和未曝光部分的图案。曝光后，可能会发生腐蚀过程，例如湿蚀刻，从而去除硬掩模的未曝光部分。在蚀刻之后，可以对硬掩模进行退火，烘烤或进行等离子体处理。

5. 发明申请

US20090104789A1 METHOD AND SYSTEM FOR IMPROVING DIELECTRIC FILM QUALITY FOR VOID FREE GAP FILL 有权
标题翻译：用于改善无电隙隙填料的电介质膜质量的方法和系统
公开(公告)号：US20090104789A1
公开(公告)日：2009-04-23
申请号：US11876541
申请日：2007-10-22
申请人： Abhijit Basu Mallick , Jeffrey C. Munro , Linlin Wang , Srinivas D. Nemani , Yi Zheng , Zheng Yuan , Dimitry Lubomirsky , Ellie Y. Yieh
发明人： Abhijit Basu Mallick , Jeffrey C. Munro , Linlin Wang , Srinivas D. Nemani , Yi Zheng , Zheng Yuan , Dimitry Lubomirsky , Ellie Y. Yieh
IPC分类号： H01L21/31
CPC分类号： H01L21/31612 , C23C16/045 , C23C16/24 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/02164 , H01L21/02274 , H01L21/0228 , H01L21/02337 , H01L21/0234 , H01L21/76837
摘要： A method of forming a silicon oxide layer on a substrate. The method includes providing a substrate and forming a first silicon oxide layer overlying at least a portion of the substrate, the first silicon oxide layer including residual water, hydroxyl groups, and carbon species. The method further includes exposing the first silicon oxide layer to a plurality of silicon-containing species to form a plurality of amorphous silicon components being partially intermixed with the first silicon oxide layer. Additionally, the method includes annealing the first silicon oxide layer partially intermixed with the plurality of amorphous silicon components in an oxidative environment to form a second silicon oxide layer on the substrate. At least a portion of amorphous silicon components are oxidized to become part of the second silicon oxide layer and unreacted residual hydroxyl groups and carbon species in the second silicon oxide layer are substantially removed.
摘要翻译：在基板上形成氧化硅层的方法。该方法包括提供衬底并形成覆盖衬底的至少一部分的第一氧化硅层，第一氧化硅层包括残留的水，羟基和碳类。该方法还包括将第一氧化硅层暴露于多个含硅物质以形成与第一氧化硅层部分混合的多个非晶硅组分。此外，该方法包括在氧化环境中将与多个非晶硅组分部分混合的第一氧化硅层退火以在衬底上形成第二氧化硅层。至少一部分非晶硅组分被氧化成第二氧化硅层的一部分，并且基本上去除了第二氧化硅层中未反应的残余羟基和碳物质。

6. 发明授权

US07541297B2 Method and system for improving dielectric film quality for void free gap fill 有权
标题翻译：改善空隙填隙电介质膜质量的方法和系统
公开(公告)号：US07541297B2
公开(公告)日：2009-06-02
申请号：US11876541
申请日：2007-10-22
申请人： Abhijit Basu Mallick , Jeffrey C. Munro , Linlin Wang , Srinivas D. Nemani , Yi Zheng , Zheng Yuan , Dimitry Lubomirsky , Ellie Y. Yieh
发明人： Abhijit Basu Mallick , Jeffrey C. Munro , Linlin Wang , Srinivas D. Nemani , Yi Zheng , Zheng Yuan , Dimitry Lubomirsky , Ellie Y. Yieh
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L21/31612 , C23C16/045 , C23C16/24 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/02164 , H01L21/02274 , H01L21/0228 , H01L21/02337 , H01L21/0234 , H01L21/76837
摘要： A method of forming a silicon oxide layer on a substrate. The method includes providing a substrate and forming a first silicon oxide layer overlying at least a portion of the substrate, the first silicon oxide layer including residual water, hydroxyl groups, and carbon species. The method further includes exposing the first silicon oxide layer to a plurality of silicon-containing species to form a plurality of amorphous silicon components being partially intermixed with the first silicon oxide layer. Additionally, the method includes annealing the first silicon oxide layer partially intermixed with the plurality of amorphous silicon components in an oxidative environment to form a second silicon oxide layer on the substrate. At least a portion of amorphous silicon components are oxidized to become part of the second silicon oxide layer and unreacted residual hydroxyl groups and carbon species in the second silicon oxide layer are substantially removed.
摘要翻译：在基板上形成氧化硅层的方法。该方法包括提供衬底并形成覆盖衬底的至少一部分的第一氧化硅层，第一氧化硅层包括残留的水，羟基和碳类。该方法还包括将第一氧化硅层暴露于多个含硅物质以形成与第一氧化硅层部分混合的多个非晶硅组分。此外，该方法包括在氧化环境中将与多个非晶硅组分部分混合的第一氧化硅层退火以在衬底上形成第二氧化硅层。至少一部分非晶硅组分被氧化成第二氧化硅层的一部分，并且基本上去除了第二氧化硅层中未反应的残余羟基和碳物质。

7. 发明申请

US20090031955A1 VACUUM CHUCKING HEATER OF AXISYMMETRICAL AND UNIFORM THERMAL PROFILE 审中-公开
标题翻译：轴对称和均匀热轮廓的真空开关加热器
公开(公告)号：US20090031955A1
公开(公告)日：2009-02-05
申请号：US11830589
申请日：2007-07-30
申请人： Siqing Lu , Balaji Chandrasekaran , Paul Edward Gee , Nitin K. Ingle , Dmitry Lubomirsky , Zheng Yuan , Ellie Y. Yieh
发明人： Siqing Lu , Balaji Chandrasekaran , Paul Edward Gee , Nitin K. Ingle , Dmitry Lubomirsky , Zheng Yuan , Ellie Y. Yieh
IPC分类号： C23C16/00 , B23B31/30
CPC分类号： C23C16/4586 , C23C16/4584 , Y10T279/11
摘要： Embodiments of a vacuum chuck having an axisymmetrical and/or more uniform thermal profile are provided herein. In some embodiments, a vacuum chuck includes a body having a support surface for supporting a substrate thereupon; a plurality of axisymmetrically arranged grooves formed in the support surface, at least some of the grooves intersecting; and a plurality of chucking holes formed through the body and within the grooves, the chucking holes for fluidly coupling the grooves to a vacuum source during operation, wherein the chucking holes are disposed in non-intersecting portions of the grooves.
摘要翻译：具有轴对称和/或更均匀的热分布的真空吸盘的实施例在此提供。在一些实施例中，真空卡盘包括具有用于支撑基板的支撑表面的主体; 形成在支撑表面中的多个轴对称布置的槽，至少一些槽相交; 以及在所述槽内形成的多个夹持孔，所述夹持孔用于在操作期间将所述槽流体耦合到真空源，其中所述夹紧孔设置在所述槽的非交叉部分中。

8. 发明授权

US07967913B2 Remote plasma clean process with cycled high and low pressure clean steps 失效
标题翻译：远程等离子清洁工艺，循环高低压清洁步骤
公开(公告)号：US07967913B2
公开(公告)日：2011-06-28
申请号：US12508381
申请日：2009-07-23
申请人： Zhong Qiang Hua , Sanjay Kamath , Young S. Lee , Ellie Y. Yieh , Hien-Minh Huu Le , Anjana M. Patel , Sudhir R. Gondhalekar
发明人： Zhong Qiang Hua , Sanjay Kamath , Young S. Lee , Ellie Y. Yieh , Hien-Minh Huu Le , Anjana M. Patel , Sudhir R. Gondhalekar
IPC分类号： B08B6/00
CPC分类号： B08B7/0035 , C23C16/4405
摘要： A remote plasma process for removing unwanted deposition build-up from one or more interior surfaces of a substrate processing chamber after processing a substrate disposed in the substrate processing chamber. In one embodiment, the substrate is transferred out of the substrate processing chamber and a flow of a fluorine-containing etchant gas is introduced into a remote plasma source where reactive species are formed. A continuous flow of the reactive species from the remote plasmas source to the substrate processing chamber is generated while a cycle of high and low pressure clean steps is repeated. During the high pressure clean step, reactive species are flown into the substrate processing chamber while pressure within the substrate processing chamber is maintained between 4-15 Torr. During the low pressure clean step, reactive species are flown into the substrate processing chamber while reducing the pressure of the substrate processing chamber by at least 50 percent of a high pressure reached in the high pressure clean step.
摘要翻译：一种远程等离子体处理，用于在处理设置在基板处理室中的基板之后从基板处理室的一个或多个内表面去除不需要的沉积物。在一个实施例中，将衬底转移出衬底处理室，并且将含氟蚀刻剂气体的流引入形成反应性物质的远程等离子体源中。产生反应物质从远程等离子体源到基底处理室的连续流动，同时重复高低压清洁步骤的循环。在高压清洁步骤期间，反应性物质流入基板处理室，同时基板处理室内的压力保持在4-15Torr之间。在低压清洁步骤期间，将反应性物质流入基板处理室，同时将基板处理室的压力降低至高压清洁步骤达到的至少50％的高压。

9. 发明申请

US20100210112A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A LANTHANUM-FAMILY-BASED OXIDE LAYER 失效
标题翻译：用于制备具有基于民族的氧化物层的半导体器件的方法
公开(公告)号：US20100210112A1
公开(公告)日：2010-08-19
申请号：US12371085
申请日：2009-02-13
申请人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
发明人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
IPC分类号： H01L21/3065
CPC分类号： H01L21/31122 , H01L21/28123 , H01L21/28167 , H01L21/31105 , H01L21/31111 , H01L21/32139 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.
摘要翻译：描述了制造具有镧族氧化物层的半导体器件的方法。具有镧族氧化物层的栅极叠层设置在基板的上方。镧族氧化物层的至少一部分被改性以形成镧族卤化物部分。用水蒸气处理除去镧族卤化物部分。

10. 发明授权

US06875558B1 Integration scheme using self-planarized dielectric layer for shallow trench isolation (STI) 失效
标题翻译：使用自平坦化介质层进行浅沟槽隔离（STI）的集成方案
公开(公告)号：US06875558B1
公开(公告)日：2005-04-05
申请号：US10049689
申请日：2000-08-16
申请人： Frederic Gaillard , Fabrice Geiger , Ellie Y. Yieh
发明人： Frederic Gaillard , Fabrice Geiger , Ellie Y. Yieh
IPC分类号： C23C16/04 , C23C16/40 , H01L21/027 , H01L21/285 , H01L21/3105 , H01L21/316 , H01L21/762 , G03F7/00
CPC分类号： C23C16/045 , C23C16/402 , H01L21/0276 , H01L21/28525 , H01L21/31053 , H01L21/31612 , H01L21/31662 , H01L21/76229
摘要： A method for forming a trench isolation structure on a substrate. The method includes applying a pad oxide layer (226) on the substrate (224), applying a polysilicon layer (228) over the pad oxide layer, and applying a CVD anti-reflective coating (ARC) (230) over the polysilicon layer. A photoresist is formed on the CVD ARC and a trenched is etched at a desired location. One embodiment provides a method for depositing a trench oxide filling layer (300) on the trenched substrate utilizing the surface sensitivity of dielectric materials such as O3/TEOS to achieve a substantially self-planarized dielectric layer. Prior problems with porous trench fill, particular near trench corners, are obviated by use of the polysilicon layer. After deposition, an oxidizing anneal can be performed to grow a thermal oxide (307) at the trench surfaces and densify the dielectric material. A chemical mechanical polish can be used to remove the excess oxide material, including the porous regions.
摘要翻译：一种在衬底上形成沟槽隔离结构的方法。该方法包括在衬底（224）上施加衬垫氧化物层（226），在衬垫氧化物层上施加多晶硅层（228），并在多晶硅层上施加CVD抗反射涂层（ARC）230。在CVD ARC上形成光致抗蚀剂，并且在期望的位置蚀刻沟槽。一个实施例提供了一种使用诸如O3 / TEOS之类的介电材料的表面灵敏度来在沟槽衬底上沉积沟槽氧化物填充层（300）以实现基本上自平坦化介电层的方法。通过使用多晶硅层来消除多孔沟槽填充，特别是靠近沟槽角的现有问题。在沉积之后，可以进行氧化退火以在沟槽表面生长热氧化物（307）并致密化电介质材料。可以使用化学机械抛光剂去除多余的氧化物材料，包括多孔区域。

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