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1. 发明申请

US20100210112A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A LANTHANUM-FAMILY-BASED OXIDE LAYER 失效
标题翻译：用于制备具有基于民族的氧化物层的半导体器件的方法
公开(公告)号：US20100210112A1
公开(公告)日：2010-08-19
申请号：US12371085
申请日：2009-02-13
申请人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
发明人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
IPC分类号： H01L21/3065
CPC分类号： H01L21/31122 , H01L21/28123 , H01L21/28167 , H01L21/31105 , H01L21/31111 , H01L21/32139 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.
摘要翻译：描述了制造具有镧族氧化物层的半导体器件的方法。具有镧族氧化物层的栅极叠层设置在基板的上方。镧族氧化物层的至少一部分被改性以形成镧族卤化物部分。用水蒸气处理除去镧族卤化物部分。

2. 发明授权

US07310785B2 Video processing architecture definition by function graph methodology 失效
标题翻译：视频处理架构通过功能图方法定义
公开(公告)号：US07310785B2
公开(公告)日：2007-12-18
申请号：US11105772
申请日：2005-04-13
申请人： Li Sha , Weimin Zeng
发明人： Li Sha , Weimin Zeng
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.
摘要翻译：公开了一种设计技术，其允许视频处理硬件设计者在设计过程的硬件架构设计阶段期间有效地采用视频处理标准（例如，H.264标准或其它此类标准）的要求。该技术消除或以其他方式减少了设计过程的资源密集型实施和验证部分的昂贵的多次通过，并允许设计者对硬件架构设计进行更改，从而确保在实施阶段的验证。

3. 发明申请

US20050207663A1 Searching method and system for best matching motion vector 审中-公开
标题翻译：用于最佳匹配运动矢量的搜索方法和系统
公开(公告)号：US20050207663A1
公开(公告)日：2005-09-22
申请号：US11064738
申请日：2005-02-23
申请人： Weimin Zeng , Li Sha , Ping Zhu
发明人： Weimin Zeng , Li Sha , Ping Zhu
IPC分类号： G06K9/36 , G06T7/20 , H04N7/12 , H04N7/26
CPC分类号： H04N19/567 , G06T7/231 , H04N19/523
摘要： The invention relates generally to compression of video data and specifically to lowering at least a cost of motion information while encoding a macroblock. According to one embodiment, the present invention searches for a matching block that lowers a cost of encoding the macroblock including the cost of encoding motion information. According to another embodiment, the present invention lowers the cost of encoding the macroblock including the cost of encoding motion information at one or more stages of a multiresolution search.
摘要翻译：本发明一般涉及视频数据的压缩，具体地涉及在对宏块进行编码时降低运动信息的成本。根据一个实施例，本发明搜索降低包含编码运动信息成本的宏块编码成本的匹配块。根据另一实施例，本发明降低了在多分辨率搜索的一个或多个阶段包括编码运动信息的成本的宏块的编码成本。

4. 发明申请

US20090003451A1 SHARED PIPELINE ARCHITECTURE FOR MOTION VECTOR PREDICTION AND RESIDUAL DECODING 审中-公开
标题翻译：用于运动矢量预测和残留解码的共享管道结构
公开(公告)号：US20090003451A1
公开(公告)日：2009-01-01
申请号：US12195344
申请日：2008-08-20
申请人： Teng Chiang Lin , Weimin Zeng
发明人： Teng Chiang Lin , Weimin Zeng
IPC分类号： H04N7/26
CPC分类号： H04N19/93 , H04N19/42 , H04N19/52
摘要： A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
摘要翻译：提供了用于H.264运动矢量预测和残差解码的共享流水线架构，以及用于标准和高清应用的主轮廓和高轮廓中的CABAC和CALVC熵的帧内预测。通过共享管道完成I型，P型和B型图像的所有运动矢量预测和残差解码。该架构能够实现更好的性能，并且比传统架构使用更少的内存。该架构可以使用例如现场可编程门阵列（FPGA）技术或专用集成电路（ASIC）或其他定制逻辑来作为片上系统或芯片集而在硬件中完全实现。

5. 发明授权

US07430238B2 Shared pipeline architecture for motion vector prediction and residual decoding 失效
标题翻译：用于运动矢量预测和残差解码的共享流水线架构
公开(公告)号：US07430238B2
公开(公告)日：2008-09-30
申请号：US11138849
申请日：2005-05-25
申请人： Teng Chiang Lin , Weimin Zeng
发明人： Teng Chiang Lin , Weimin Zeng
IPC分类号： H04N7/12
CPC分类号： H04N19/93 , H04N19/42 , H04N19/52
摘要： A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
摘要翻译：提供了用于H.264运动矢量预测和残差解码的共享流水线架构，以及用于标准和高清应用的主轮廓和高轮廓中的CABAC和CALVC熵的帧内预测。通过共享管道完成I型，P型和B型图像的所有运动矢量预测和残差解码。该架构能够实现更好的性能，并且比传统架构使用更少的内存。该架构可以使用例如现场可编程门阵列（FPGA）技术或专用集成电路（ASIC）或其他定制逻辑来作为片上系统或芯片集而在硬件中完全实现。

6. 发明申请

US20060126740A1 Shared pipeline architecture for motion vector prediction and residual decoding 失效
标题翻译：用于运动矢量预测和残差解码的共享流水线架构
公开(公告)号：US20060126740A1
公开(公告)日：2006-06-15
申请号：US11138849
申请日：2005-05-25
申请人： Teng Lin , Weimin Zeng
发明人： Teng Lin , Weimin Zeng
IPC分类号： H04N11/02 , H04N11/04 , H04B1/66 , H04N7/12
CPC分类号： H04N19/93 , H04N19/42 , H04N19/52
摘要： A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
摘要翻译：提供了用于H.264运动矢量预测和残差解码的共享流水线架构，以及用于标准和高清应用的主轮廓和高轮廓中的CABAC和CALVC熵的帧内预测。通过共享管道完成I型，P型和B型图像的所有运动矢量预测和残差解码。该架构能够实现更好的性能，并且比传统架构使用更少的内存。该架构可以使用例如现场可编程门阵列（FPGA）技术或专用集成电路（ASIC）或其他定制逻辑来作为片上系统或芯片集而在硬件中完全实现。

7. 发明申请

US20060126726A1 Digital signal processing structure for decoding multiple video standards 审中-公开
标题翻译：用于解码多个视频标准的数字信号处理结构
公开(公告)号：US20060126726A1
公开(公告)日：2006-06-15
申请号：US11137971
申请日：2005-05-25
申请人： Teng Lin , Hongjun Yuan , Weimin Zeng , Liang Peng
发明人： Teng Lin , Hongjun Yuan , Weimin Zeng , Liang Peng
IPC分类号： H04N11/04 , H04N7/12 , H04N11/02 , H04B1/66
CPC分类号： H04N19/436 , H04N19/12 , H04N19/136 , H04N19/172 , H04N19/423 , H04N19/44 , H04N19/61
摘要： In one embodiment, a DSP structure includes four main sections: DEQ, IDCT for row, IDCT for column, and motion compensation. The data input sequence is organized in such a way to facilitate the data loading into hardware structures for row IDCT and column IDCT. Two types of decoding flows are enabled by the DSP structure: H.264 decoding flows (e.g., dequantization, inverse discrete Hadamard transform, intra prediction, and motion decompensation), and non-H.264 decoding flows (e.g., dequantization, row inverse discrete cosine transformation, column inverse discrete cosine transformation, and motion decompensation). The non-H.264 decoding flow can be used for standards such as MPEG1/2/4, H.263, Microsoft WMV9, and Sony Digital Video.
摘要翻译：在一个实施例中，DSP结构包括四个主要部分：DEQ，行的IDCT，列的IDCT和运动补偿。数据输入序列以便于将数据加载到行IDCT和列IDCT的硬件结构中的方式组织。通过DSP结构启用两种类型的解码流程：H.264解码流（例如，逆量化，逆离散Hadamard变换，帧内预测和运动失真），以及非H.264解码流（例如，逆量化，行反向离散余弦变换，列逆离散余弦变换和运动失真）。非H.264解码流可用于MPEG1 / 2/4，H.263，Microsoft WMV9和Sony Digital Video等标准。

8. 发明申请

US20060126725A1 Automated test vector generation for complicated video system verification 审中-公开
标题翻译：用于复杂视频系统验证的自动测试矢量生成
公开(公告)号：US20060126725A1
公开(公告)日：2006-06-15
申请号：US11123582
申请日：2005-05-05
申请人： Weimin Zeng , Yaojun Luo , Yu Tian
发明人： Weimin Zeng , Yaojun Luo , Yu Tian
IPC分类号： H04N11/04 , H04B1/66 , H04N11/02 , H04N7/12
CPC分类号： H04N17/004 , H04N19/61 , H04N19/70
摘要： According to one embodiment, the present invention generates a test vector for verification of a video encoder or decoder by encoding video data using a permissible combination of parameters. One embodiment of the present invention provides for verification of a video decoder by performing at least one video decoding operation and comparing a resulting partially or fully decoded test vector to an expected value. Another embodiment of the present invention provides for verification of a video encoder by performing at least one video encoding operation using a selected combination of parameters, and comparing a resulting partially or fully encoded test vector to an expected value.
摘要翻译：根据一个实施例，本发明通过使用允许的参数组合对视频数据进行编码来生成用于验证视频编码器或解码器的测试向量。本发明的一个实施例通过执行至少一个视频解码操作并将得到的部分或完全解码的测试向量与预期值进行比较来提供视频解码器的验证。本发明的另一实施例提供了通过使用所选择的参数组合执行至少一个视频编码操作并且将得到的部分或完全编码的测试向量与预期值进行比较来验证视频编码器。

9. 发明申请

US20050249293A1 Noise filter for video processing 失效
标题翻译：用于视频处理的噪声滤波器
公开(公告)号：US20050249293A1
公开(公告)日：2005-11-10
申请号：US10959333
申请日：2004-10-05
申请人： Weimin Zeng , Li Alpha , Ping Zhu
发明人： Weimin Zeng , Li Alpha , Ping Zhu
IPC分类号： H04N5/21 , H04N7/26 , H04N5/217
CPC分类号： H04N5/21 , H04N19/117 , H04N19/14
摘要： A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blocks are provided to the cost calculator determines a cost for each of the coefficients in the block using the cost table and the costs are summed. The cost comparator compares the total to a threshold, and filters the coefficients using the coefficient filter if the total is greater a preset threshold. The noise filter to the VLC unit then outputs the filter data.
摘要翻译：用于视频处理系统的噪声滤波器包括块选择器，成本计算器，成本表，成本比较器和系数滤波器。块选择器被耦合以从量化单元接收数据并且选择用于额外滤波的块。所选择的块被提供给成本计算器使用成本表确定块中的每个系数的成本，并且将成本相加。成本比较器将总和比较为阈值，并且如果总数大于预设阈值，则使用系数滤波器对系数进行滤波。然后，VLC单元的噪声滤波器输出滤波器数据。

10. 发明授权

US08101525B2 Method for fabricating a semiconductor device having a lanthanum-family-based oxide layer 失效
标题翻译：具有镧系氧化物层的半导体装置的制造方法
公开(公告)号：US08101525B2
公开(公告)日：2012-01-24
申请号：US12371085
申请日：2009-02-13
申请人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
发明人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31122 , H01L21/28123 , H01L21/28167 , H01L21/31105 , H01L21/31111 , H01L21/32139 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.
摘要翻译：描述了制造具有镧族氧化物层的半导体器件的方法。具有镧族氧化物层的栅极叠层设置在基板的上方。镧族氧化物层的至少一部分被改性以形成镧族卤化物部分。用水蒸气处理除去镧族卤化物部分。

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