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1. 发明授权

US07528051B2 Method of inducing stresses in the channel region of a transistor 失效
标题翻译：在晶体管的沟道区域中产生应力的方法
公开(公告)号：US07528051B2
公开(公告)日：2009-05-05
申请号：US10846734
申请日：2004-05-14
申请人： Reza Arghavani , Zheng Yuan , Ellie Y. Yieh , Shankar Venkataraman , Nitin K. Ingle
发明人： Reza Arghavani , Zheng Yuan , Ellie Y. Yieh , Shankar Venkataraman , Nitin K. Ingle
IPC分类号： H01L21/76
CPC分类号： H01L29/6656 , H01L21/823807 , H01L29/6659 , H01L29/7833 , H01L29/7846
摘要： A method of fabricating a semiconductor device, where the method includes forming a transistor on a substrate, where the transistor includes a channel region configured to conduct charge between a source region and a drain region, forming a trench adjacent to the transistor, depositing a material on the substrate and within the trench, and annealing the material, where the material is tensile following the annealing and creates a tensile stress in the channel region. Also, a method of forming a trench isolation in a semiconductor device, where the method includes forming a trench in a substrate, forming a material within the trench at a lower deposition rate, forming the material on the substrate at a higher deposition rate after the depositing of the material within the trench, and annealing the material, where after the annealing the material in the trench is tensile.
摘要翻译：一种制造半导体器件的方法，其中所述方法包括在衬底上形成晶体管，其中所述晶体管包括被配置为在源极区域和漏极区域之间传导电荷的沟道区域，形成与所述晶体管相邻的沟槽，在衬底上和沟槽内，并对材料进行退火，其中材料在退火之后是拉伸的，并且在沟道区域中产生拉伸应力。另外，在半导体器件中形成沟槽隔离的方法，其中所述方法包括在衬底中形成沟槽，以较低的沉积速率在沟槽内形成材料，在衬底上以更高的沉积速率在衬底上形成材料在沟槽内沉积材料并退火材料，其中在退火之后，沟槽中的材料是拉伸的。

2. 发明授权

US07087497B2 Low-thermal-budget gapfill process 有权
标题翻译：低热量预算的填隙过程
公开(公告)号：US07087497B2
公开(公告)日：2006-08-08
申请号：US10793559
申请日：2004-03-04
申请人： Zheng Yuan , Reza Arghavani , Ellie Y Yieh , Shankar Venkataraman
发明人： Zheng Yuan , Reza Arghavani , Ellie Y Yieh , Shankar Venkataraman
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , C23C16/403 , C23C16/45536 , C23C16/45544 , H01J37/32009 , H01L21/02178 , H01L21/0228 , H01L21/32055 , H01L21/67017 , H01L21/6719 , H01L21/763
摘要： A low-thermal-budget gapfill process is provided for filling a gap formed between two adjacent raised features on a strained-silicon substrate as part of a shallow-trench-isolation process. An electrically insulating liner is deposited using atomic-layer deposition and polysilicon is deposited over the electrically insulating liner, with both stages being conducted at temperatures below 700° C.
摘要翻译：提供了一种低热预算的间隙填充方法，用于填充在应变硅衬底上形成的两个相邻隆起特征之间的间隙，作为浅沟槽隔离工艺的一部分。使用原子层沉积沉积电绝缘衬垫，并且将多晶硅沉积在电绝缘衬垫上，其中两个阶段在低于700℃的温度下进行。

3. 发明授权

US07033945B2 Gap filling with a composite layer 失效
标题翻译：间隙填充复合层
公开(公告)号：US07033945B2
公开(公告)日：2006-04-25
申请号：US10857829
申请日：2004-06-01
申请人： Jeong Soo Byun , Zheng Yuan , Shankar Venkataraman , M. Ziaul Karim , Thanh N. Pham , Ellie Y. Yieh
发明人： Jeong Soo Byun , Zheng Yuan , Shankar Venkataraman , M. Ziaul Karim , Thanh N. Pham , Ellie Y. Yieh
IPC分类号： H01L21/311
CPC分类号： H01L21/76224
摘要： A method of filling a gap formed between adjacent raised surfaces on a substrate. In one embodiment the method comprises depositing a boron-doped silica glass (BSG) layer over the substrate to partially fill the gap using a thermal CVD process; exposing the BSG layer to a steam ambient at a temperature above the BSG layer's Eutectic temperature; removing an upper portion of the BSG layer by exposing the layer to a fluorine-containing etchant; and depositing an undoped silica glass (USG) layer over the BSG layer to fill the remainder of the gap.
摘要翻译：填充在基板上相邻的凸起表面之间形成的间隙的方法。在一个实施例中，该方法包括在衬底上沉积硼掺杂石英玻璃（BSG）层，以使用热CVD工艺部分填充间隙; 在高于BSG层的共晶温度的温度下将BSG层暴露于蒸汽环境; 通过将层暴露于含氟蚀刻剂来除去BSG层的上部; 以及在BSG层上沉积未掺杂的二氧化硅玻璃（USG）层以填补间隙的剩余部分。

4. 发明授权

US07431967B2 Limited thermal budget formation of PMD layers 失效
标题翻译：有限的热预算形成PMD层
公开(公告)号：US07431967B2
公开(公告)日：2008-10-07
申请号：US10757770
申请日：2004-01-14
申请人： Zheng Yuan , Shankar Venkataraman , Cary Ching , Shang Wong , Kevin Mikio Mukai , Nitin K. Ingle
发明人： Zheng Yuan , Shankar Venkataraman , Cary Ching , Shang Wong , Kevin Mikio Mukai , Nitin K. Ingle
IPC分类号： C23C16/00 , C23C14/00 , C23C16/22 , H01L21/302 , H01L21/461
CPC分类号： C23C16/401 , C23C16/45512 , C23C16/45523 , C23C16/52 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31608 , H01L21/31625 , H01L21/76837
摘要： A method of filling a gap on a substrate includes providing flows of silicon-containing processing gas oxidizing processing gas, and phosphorous-containing processing gas to a chamber housing the substrate and depositing a first portion of a P-doped silicon oxide film as a substantially conformal layer in the gap by causing a reaction among the processing gases and varying over time a ratio of the gases. The temperature of the substrate is maintained below about 500° C. throughout deposition of the conformal layer. The method also includes depositing a second portion of the P-doped silicon oxide film as a bulk layer by maintaining the ratio of the gases substantially constant throughout deposition of the bulk layer. The temperature of the substrate is maintained below about 500° C. throughout deposition of the bulk layer.
摘要翻译：在衬底上填充间隙的方法包括提供含硅处理气体氧化处理气体和含磷处理气体的流向容纳衬底的腔室，并将P掺杂氧化硅膜的第一部分基本上通过引起处理气体之间的反应并随时间改变气体的比例，间隙中的保形层。在保形层的沉积过程中，基板的温度保持在约500℃以下。该方法还包括通过在本体层的整个沉积期间保持气体的比率基本恒定来沉积P掺杂氧化硅膜的第二部分作为本体层。在本体层的整个沉积过程中，衬底的温度保持在约500℃以下。

5. 发明授权

US07674727B2 Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill 有权
标题翻译： TEOS /臭氧CVD的一氧化二氮退火以改善间隙填料
公开(公告)号：US07674727B2
公开(公告)日：2010-03-09
申请号：US11549919
申请日：2006-10-16
申请人： Zheng Yuan , Reza Arghavani , Shankar Venkataraman
发明人： Zheng Yuan , Reza Arghavani , Shankar Venkataraman
IPC分类号： H01L21/31
CPC分类号： H01L21/31612 , C23C16/045 , C23C16/401 , C23C16/402 , C23C16/45512 , C23C16/45523 , C23C16/52 , C23C16/56 , H01L21/02129 , H01L21/02164 , H01L21/02216 , H01L21/02271 , H01L21/02312 , H01L21/76224 , H01L21/76822 , H01L21/76828 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes varying over time a ratio of the (silicon-containing processing gas):(oxidizing gas). The method also includes exposing the substrate to nitrous oxide at a temperature less than about 900° C. to anneal the deposited film.
摘要翻译：填充由衬底上的相邻凸起特征限定的间隙的方法包括提供含硅处理气体流到容纳衬底并且向腔室提供氧化气体流的腔室。该方法还包括随时间变化（含硅处理气体）：氧化气体的比例。该方法还包括在小于约900℃的温度下将衬底暴露于一氧化二氮以使沉积的膜退火。

6. 发明申请

US20070059896A1 NITROUS OXIDE ANNEAL OF TEOS/OZONE CVD FOR IMPROVED GAPFILL 有权
标题翻译：氧化氮氧化物氧化铝氧化铝改进的GAPFILL CVD
公开(公告)号：US20070059896A1
公开(公告)日：2007-03-15
申请号：US11549919
申请日：2006-10-16
申请人： Zheng Yuan , Reza Arghavani , Shankar Venkataraman
发明人： Zheng Yuan , Reza Arghavani , Shankar Venkataraman
IPC分类号： H01L21/76 , H01L21/31
CPC分类号： H01L21/31612 , C23C16/045 , C23C16/401 , C23C16/402 , C23C16/45512 , C23C16/45523 , C23C16/52 , C23C16/56 , H01L21/02129 , H01L21/02164 , H01L21/02216 , H01L21/02271 , H01L21/02312 , H01L21/76224 , H01L21/76822 , H01L21/76828 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes varying over time a ratio of the (silicon-containing processing gas):(oxidizing gas). The method also includes exposing the substrate to nitrous oxide at a temperature less than about 900° C. to anneal the deposited film.
摘要翻译：填充由衬底上的相邻凸起特征限定的间隙的方法包括提供含硅处理气体流到容纳衬底并且向腔室提供氧化气体流的腔室。该方法还包括随时间变化（含硅处理气体）：氧化气体的比例。该方法还包括在小于约900℃的温度下将衬底暴露于一氧化二氮以使沉积的膜退火。

7. 发明申请

US20050255667A1 Method of inducing stresses in the channel region of a transistor 失效
标题翻译：在晶体管的沟道区域中产生应力的方法
公开(公告)号：US20050255667A1
公开(公告)日：2005-11-17
申请号：US10846734
申请日：2004-05-14
申请人： Reza Arghavani , Zheng Yuan , Ellie Yieh , Shankar Venkataraman , Nitin Ingle
发明人： Reza Arghavani , Zheng Yuan , Ellie Yieh , Shankar Venkataraman , Nitin Ingle
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8238 , H01L29/00 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/823807 , H01L29/6659 , H01L29/7833 , H01L29/7846
摘要： A method of fabricating a semiconductor device, where the method includes forming on a transistor on a substrate, where the transistor includes a channel region configured to conduct charge between a source region and a drain region, forming a trench adjacent to the transistor, depositing a material on the substrate and within the trench, and annealing the material, where the material is tensile following the annealing and creates a tensile stress in the channel region. Also, a method of forming a trench isolation in a semiconductor device, where the method includes forming a trench in a substrate, forming a material within the trench at a lower deposition rate, forming the material on the substrate at a higher deposition rate after the depositing of the material within the trench, and annealing the material, where after the annealing the material in the trench is tensile.
摘要翻译：一种制造半导体器件的方法，其中所述方法包括在衬底上的晶体管上形成晶体管，其中所述晶体管包括被配置为在源极区域和漏极区域之间导电的沟道区域，形成与所述晶体管相邻的沟槽，材料在衬底上并在沟槽内，并退火材料，其中材料在退火之后是拉伸的，并且在沟道区域中产生拉伸应力。另外，在半导体器件中形成沟槽隔离的方法，其中所述方法包括在衬底中形成沟槽，以较低的沉积速率在沟槽内形成材料，在衬底上以更高的沉积速率在衬底上形成材料在沟槽内沉积材料并退火材料，其中在退火之后，沟槽中的材料是拉伸的。

8. 发明申请

US20050196929A1 Low-thermal-budget gapfill process 有权
标题翻译：低热量预算的填隙过程
公开(公告)号：US20050196929A1
公开(公告)日：2005-09-08
申请号：US10793559
申请日：2004-03-04
申请人： Zheng Yuan , Reza Arghavani , Ellie Yieh , Shankar Venkataraman
发明人： Zheng Yuan , Reza Arghavani , Ellie Yieh , Shankar Venkataraman
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , C23C16/403 , C23C16/45536 , C23C16/45544 , H01J37/32009 , H01L21/02178 , H01L21/0228 , H01L21/32055 , H01L21/67017 , H01L21/6719 , H01L21/763
摘要： A low-thermal-budget gapfill process is provided for filling a gap formed between two adjacent raised features on a strained-silicon substrate as part of a shallow-trench-isolation process. An electrically insulating liner is deposited using atomic-layer deposition and polysilicon is deposited over the electrically insulating liner, with both stages being conducted at temperatures below 700° C.
摘要翻译：提供了一种低热预算的间隙填充方法，用于填充在应变硅衬底上形成的两个相邻凸起特征之间的间隙，作为浅沟槽隔离工艺的一部分。使用原子层沉积沉积电绝缘衬垫，并且将多晶硅沉积在电绝缘衬垫上，其中两个阶段在低于700℃的温度下进行。

9. 发明授权

US07141483B2 Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill 有权
标题翻译： TEOS /臭氧CVD的一氧化二氮退火以改善间隙填料
公开(公告)号：US07141483B2
公开(公告)日：2006-11-28
申请号：US10757771
申请日：2004-01-14
申请人： Zheng Yuan , Reza Arghavani , Shankar Venkataraman
发明人： Zheng Yuan , Reza Arghavani , Shankar Venkataraman
IPC分类号： H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/31612 , C23C16/045 , C23C16/401 , C23C16/402 , C23C16/45512 , C23C16/45523 , C23C16/52 , C23C16/56 , H01L21/02129 , H01L21/02164 , H01L21/02216 , H01L21/02271 , H01L21/02312 , H01L21/76224 , H01L21/76822 , H01L21/76828 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes depositing a first portion of a film as a substantially conformal layer in the gap by causing a reaction between the silicon-containing processing gas and the oxidizing gas. Depositing the conformal layer includes varying over time a ratio of the (silicon-containing processing gas):(oxidizing gas) and regulating the chamber to a pressure in a range from about 200 torr to about 760 torr throughout deposition of the conformal layer. The method also includes depositing a second portion of the film as a bulk layer. Depositing a second portion of the film includes maintaining the ratio of the (silicon-containing processing gas):(oxidizing gas) substantially constant throughout deposition of the bulk layer and regulating the chamber to a pressure in a range from about 200 torr to about 760 torr throughout deposition of the bulk layer. The method also includes exposing the substrate to nitrous oxide at a temperature less than about 900° C. to anneal the deposited film.
摘要翻译：填充由衬底上的相邻凸起特征限定的间隙的方法包括提供含硅处理气体流到容纳衬底并且向腔室提供氧化气体流的腔室。该方法还包括通过引起含硅处理气体和氧化气体之间的反应，将膜的第一部分沉积在间隙中作为基本上共形的层。沉积保形层包括随着时间的推移，在沉积共形层的过程中，（含硅处理气体）:(氧化气体）的比例和室的调节范围为约200托至约760托的压力。该方法还包括将膜的第二部分沉积为本体层。沉积薄膜的第二部分包括在沉积主体层期间保持（含硅处理气体）:(氧化气体）的比例基本上恒定，并将室调节到约200托至约760的范围内的压力托盘在整个堆积层的沉积中。该方法还包括在小于约900℃的温度下将衬底暴露于一氧化二氮以使沉积的膜退火。

10. 发明申请

US20090208880A1 PROCESS SEQUENCE FOR FORMATION OF PATTERNED HARD MASK FILM (RFP) WITHOUT NEED FOR PHOTORESIST OR DRY ETCH 有权
标题翻译：用于形成图形硬片（RFP）的过程序列，不需要用于光刻胶或干蚀刻
公开(公告)号：US20090208880A1
公开(公告)日：2009-08-20
申请号：US12034000
申请日：2008-02-20
申请人： SRINIVAS D. NEMANI , Shankar Venkataraman , Ellie Y. Yieh
发明人： SRINIVAS D. NEMANI , Shankar Venkataraman , Ellie Y. Yieh
IPC分类号： G03F7/00 , C23F1/00
CPC分类号： G03F7/0757 , H01L21/02164 , H01L21/3086 , H01L21/3105 , H01L21/31111 , H01L21/31612 , H01L21/6719 , H01L21/67207
摘要： Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.
摘要翻译：根据本发明的一个实施方案公开了使用紫外光图案化硬掩膜的方法和系统。本发明的实施例减轻了沉积和蚀刻光刻胶的处理问题，以产生硬掩模图案。首先将诸如氧化硅的硬掩模层沉积在沉积室内的衬底上。在一些情况下，硬掩模层在沉积之后被烘烤或退火。之后，硬掩模层的一部分用紫外线照射。紫外光产生硬掩模材料的暴露和未曝光部分的图案。曝光后，可能会发生腐蚀过程，例如湿蚀刻，从而去除硬掩模的未曝光部分。在蚀刻之后，可以对硬掩模进行退火，烘烤或进行等离子体处理。

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