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1. 发明授权

US5754482A Memory using undecoded precharge for high speed data sensing 失效
标题翻译：内存使用未编码的预充电用于高速数据传感
公开(公告)号：US5754482A
公开(公告)日：1998-05-19
申请号：US845097
申请日：1997-04-21
申请人： Jeffrey Yangming Su , Bruce Lee Morton , Chad Steven Gallun
发明人： Jeffrey Yangming Su , Bruce Lee Morton , Chad Steven Gallun
IPC分类号： G11C16/06 , G11C7/12 , G11C16/24 , G11C16/28 , G11C16/04
CPC分类号： G11C16/28 , G11C16/24 , G11C7/12
摘要： A memory (400) returns all bit lines to a predetermined voltage level optimum for subsequent fast sensing. The memory (400) includes precharge circuitry (106, 108, 110) which begins the precharge operation during the latching phase of a prior access. The precharge circuitry (106, 108, 110) precharges all bit lines, rather than a selected bit line, to the predetermined voltage level prior to address decoding. In order to prevent "walk-up", the memory (400) includes circuitry such as a switched capacitor (138, 140) which draws current from the bit lines to reduce the voltage on a bit line which drove a logic high level in an earlier cycle or which had an increased voltage due to capacitive cross-coupling to an adjacent bit line. The memory (400) may also include devices such as transmission gates (142, 144, 146) to couple together adjacent bit lines and thereby more evenly distribute the precharging.
摘要翻译：存储器（400）将所有位线返回到用于随后的快速感测最佳的预定电压电平。存储器（400）包括在先前访问的锁存阶段期间开始预充电操作的预充电电路（106,108,110）。在地址解码之前，预充电电路（106,108,110）将所有位线而不是所选择的位线预充电到预定电压电平。为了防止“走动”，存储器（400）包括诸如开关电容器（138,140）的电路，其从位线吸取电流以减少位线上的电压，从而驱动逻辑高电平或者由于与相邻位线的电容性交叉耦合而具有增加的电压。存储器（400）还可以包括诸如用于将相邻位线耦合在一起的传输门（142,144,146）的装置，从而更均匀地分配预充电。

2. 发明申请

US20110235430A1 MEMORY DEVICE AND METHOD 有权
标题翻译：存储器件和方法
公开(公告)号：US20110235430A1
公开(公告)日：2011-09-29
申请号：US13154616
申请日：2011-06-07
申请人： Bruce Lee Morton , Michael VanBuskirk
发明人： Bruce Lee Morton , Michael VanBuskirk
IPC分类号： G11C16/28
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C7/18 , G11C8/12 , G11C16/0483 , G11C16/26
摘要： During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.
摘要翻译：在第一读取周期的第一部分期间，确定读出放大器的第一输入是在读周期的第一部分期间基于存储单元的状态接收信息，并且确定第一输入处的电导基本相等在第一部分期间到感测放大器的第二输入处的电导。多个NAND串模块连接到存储器件的全局位线，该存储器件包括形成多个NAND串和缓冲器的存储器列。

3. 发明授权

US09530463B1 Memory device and method thereof 有权
公开(公告)号：US09530463B1
公开(公告)日：2016-12-27
申请号：US14815158
申请日：2015-07-31
申请人： Bruce Lee Morton
发明人： Bruce Lee Morton
IPC分类号： G11C7/00 , G11C7/06 , G11C7/12
CPC分类号： G11C7/062 , G11C7/06 , G11C7/067 , G11C7/1051 , G11C7/12 , G11C7/22 , G11C2207/068
摘要： A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.

4. 发明申请

US20090303793A1 MEMORY DEVICE AND METHOD 有权
公开(公告)号：US20090303793A1
公开(公告)日：2009-12-10
申请号：US12134898
申请日：2008-06-06
申请人： Bruce Lee Morton , Michael VanBuskirk
发明人： Bruce Lee Morton , Michael VanBuskirk
IPC分类号： G11C16/26
CPC分类号： G11C16/0483 , G11C16/26 , H01L27/115 , H01L27/11519 , H01L27/11565
摘要： During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

5. 发明授权

US6128224A Method and apparatus for writing an erasable non-volatile memory 有权
标题翻译：用于写入可擦除非易失性存储器的方法和装置
公开(公告)号：US6128224A
公开(公告)日：2000-10-03
申请号：US289699
申请日：1999-04-09
申请人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout , Eric Boulian
发明人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout , Eric Boulian
IPC分类号： G11C16/02 , G11C16/00 , G11C16/10 , G11C16/06
CPC分类号： G11C16/10
摘要： A method for writing data to non-volatile memory (50) involves alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). After writing, a verify erase (VE) operation and a verify program (VP) operation are performed to determine if multiple cycles are necessary. The method also permits refreshing data in the array without transferring the data onto a data bus for improved security. In one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete. The memory cell structure allows isolation of each bit in the array to avoid adverse effects on neighbor bits.
摘要翻译：一种将数据写入非易失性存储器（50）的方法包括交替地将编程和擦除电压施加到存储器单元的控制门字线。写入包括存储器阵列（56）中的编程和擦除位（30,31，...，32,33）。在写入之后，执行验证擦除（VE）操作和验证程序（VP）操作以确定是否需要多个周期。该方法还允许在阵列中刷新数据而不将数据传输到数据总线上以提高安全性。在一个实施例中，通过向所选字线的漏极选择提供高电压，同时向其它字线的漏极选择提供低电压来写入三晶体管EEPROM。编程和擦除电压以周期的形式施加到所选字线的控制栅极字线，直到写入完成。存储单元结构允许隔离阵列中的每个位，以避免对相邻位的不利影响。

6. 发明授权

US08339873B1 Memory device and method thereof 有权
标题翻译：存储器件及其方法
公开(公告)号：US08339873B1
公开(公告)日：2012-12-25
申请号：US12768282
申请日：2010-04-27
申请人： Bruce Lee Morton
发明人： Bruce Lee Morton
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C7/06 , G11C2207/002 , G11C2207/068
摘要： A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.
摘要翻译：读出放大器的第一输入端连接到第一位线，读出放大器的第二输入端连接到第二位线，读出放大器的第三输入端耦合到第三位线。感测放大器基于经由第一，第二和第三位线提供给读出放大器的信息，在输出端提供连接到第一位线的存储单元的存储状态的指示符。

7. 发明授权

US07838342B2 Memory device and method 有权
标题翻译：内存设备和方法
公开(公告)号：US07838342B2
公开(公告)日：2010-11-23
申请号：US12134902
申请日：2008-06-06
申请人： Bruce Lee Morton , Michael VanBuskirk
发明人： Bruce Lee Morton , Michael VanBuskirk
IPC分类号： H01L21/82
CPC分类号： G11C16/0483 , G11C16/08 , H01L27/115 , H01L27/11519 , H01L27/11565 , Y10T29/49002
摘要： During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.
摘要翻译：在第一读取周期的第一部分期间，确定读出放大器的第一输入是在读周期的第一部分期间基于存储单元的状态接收信息，并且确定第一输入处的电导基本相等在第一部分期间到感测放大器的第二输入处的电导。多个NAND串模块连接到存储器件的全局位线，该存储器件包括形成多个NAND串和缓冲器的存储器列。

8. 发明授权

US09099169B1 Memory device and method thereof 有权
标题翻译：存储器件及其方法
公开(公告)号：US09099169B1
公开(公告)日：2015-08-04
申请号：US13481924
申请日：2012-05-28
申请人： Bruce Lee Morton
发明人： Bruce Lee Morton
IPC分类号： G11C7/00 , G11C7/10 , G11C7/22 , G11C7/12
CPC分类号： G11C7/062 , G11C7/06 , G11C7/067 , G11C7/1051 , G11C7/12 , G11C7/22 , G11C2207/068
摘要： A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.
摘要翻译：读出放大器的第一输入端连接到第一位线，读出放大器的第二输入端连接到第二位线，读出放大器的第三输入端耦合到第三位线。感测放大器基于经由第一，第二和第三位线提供给读出放大器的信息，在输出端提供连接到第一位线的存储单元的存储状态的指示符。

9. 发明授权

US07830716B2 Non-volatile memory string module with buffer and method 有权
标题翻译：具有缓冲区和方法的非易失性存储器字符串模块
公开(公告)号：US07830716B2
公开(公告)日：2010-11-09
申请号：US12134898
申请日：2008-06-06
申请人： Bruce Lee Morton , Michael VanBuskirk
发明人： Bruce Lee Morton , Michael VanBuskirk
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26 , H01L27/115 , H01L27/11519 , H01L27/11565
摘要： During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.
摘要翻译：在第一读取周期的第一部分期间，确定读出放大器的第一输入是在读周期的第一部分期间基于存储单元的状态接收信息，并且确定第一输入处的电导基本相等在第一部分期间到感测放大器的第二输入处的电导。多个NAND串模块连接到存储器件的全局位线，该存储器件包括形成多个NAND串和缓冲器的存储器列。

10. 发明申请

US20090303795A1 MEMORY DEVICE AND METHOD 有权
公开(公告)号：US20090303795A1
公开(公告)日：2009-12-10
申请号：US12134902
申请日：2008-06-06
申请人： Bruce Lee Morton , Michael VanBuskirk
发明人： Bruce Lee Morton , Michael VanBuskirk
IPC分类号： G11C16/04 , H01S4/00 , G11C7/00 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/08 , H01L27/115 , H01L27/11519 , H01L27/11565 , Y10T29/49002
摘要： During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

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