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1. 发明授权

US6075727A Method and apparatus for writing an erasable non-volatile memory 失效
标题翻译：用于写入可擦除非易失性存储器的方法和装置
公开(公告)号：US6075727A
公开(公告)日：2000-06-13
申请号：US124466
申请日：1998-07-29
申请人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout
发明人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout
IPC分类号： G11C16/10 , G11C16/06 , G11C7/00 , G11C16/04
CPC分类号： G11C16/10
摘要： A method for writing to a bit of a non-volatile memory (50) by alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). Upon completion of the write operation a verify erase (VE) indication and a verify program (VP) indication are provided to a memory controller (58), which then determines if multiple cycles are necessary. The configuration of the memory cell allows isolation of each bit in the memory array to avoid effects of writes to neighbor bits. According to one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete.
摘要翻译：一种通过交替地向存储器单元的控制栅极字线施加编程和擦除电压来写入非易失性存储器（50）的一种方法。写入包括存储器阵列（56）中的编程和擦除位（30,31，...，32,33）。在写入操作完成时，将验证擦除（VE）指示和验证程序（VP）指示提供给存储器控制器（58），存储器控制器（58）然后确定是否需要多个周期。存储器单元的配置允许隔离存储器阵列中的每个位以避免对相邻位的写入的影响。根据一个实施例，通过向所选字线的漏极选择提供高电压，同时向其它字线的漏极选择提供低电压来写入三晶体管EEPROM。编程和擦除电压以周期的形式施加到所选字线的控制栅极字线，直到写入完成。

2. 发明授权

US5258754A Circuit array for operating a liquid-crystal display (LCD) 失效
标题翻译：用于操作液晶显示器（LCD）的电路阵列
公开(公告)号：US5258754A
公开(公告)日：1993-11-02
申请号：US533592
申请日：1990-06-05
申请人： Peter Broderick , Graham Stout
发明人： Peter Broderick , Graham Stout
IPC分类号： G09G3/18
CPC分类号： G09G3/18
摘要： The invention relates to a circuit array for operating a liquid-crystal display in the time-division multiplexing mode, the display having at least one backplane and several segments. The circuit array includes a microprocessor having a first pulse generator, a shift register array storing data signals supplied to the circuit array, this shift register array having a number of stages corresponding to the number of segments, and driving stages which generate segment pulse sequences for the segments in accordance with the supplied data signals. In accordance with the invention, the microprocessor supplies the data signals to the shift register array via a first interface, the shift register array being designed as a cyclic shift register with each register point of the shift register array being clearly allocated to a segment. In addition, the microprocessor supplies control data, particularly data determining the time multiplexing rate, to a second interface having a decoder. The decoded control data is passed to a pulse generator that generates a pulse sequence corresponding to a backplane pulse sequence, excepting the voltage level. Finally, each driving stage is supplied with a pulse sequence in order to generate the segment pulse sequences corresponding to the contents of the register points of the cyclic shift register.
摘要翻译：本发明涉及一种用于以时分多路复用模式操作液晶显示器的电路阵列，该显示器具有至少一个背板和若干分段。电路阵列包括具有第一脉冲发生器的微处理器，存储提供给电路阵列的数据信号的移位寄存器阵列，该移位寄存器阵列具有对应于段数的级数，驱动级产生段脉冲序列，根据提供的数据信号的段。根据本发明，微处理器经由第一接口将数据信号提供给移位寄存器阵列，移位寄存器阵列被设计为循环移位寄存器，移位寄存器阵列的每个寄存器点被清楚地分配给段。此外，微处理器向具有解码器的第二接口提供控制数据，特别是确定时间复用速率的数据。解码的控制数据被传送到脉冲发生器，脉冲发生器产生与背板脉冲序列相对应的脉冲序列，除了电压电平。最后，向每个驱动级提供脉冲序列，以产生与循环移位寄存器的寄存器点的内容相对应的段脉冲序列。

3. 发明授权

US6128224A Method and apparatus for writing an erasable non-volatile memory 有权
标题翻译：用于写入可擦除非易失性存储器的方法和装置
公开(公告)号：US6128224A
公开(公告)日：2000-10-03
申请号：US289699
申请日：1999-04-09
申请人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout , Eric Boulian
发明人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout , Eric Boulian
IPC分类号： G11C16/02 , G11C16/00 , G11C16/10 , G11C16/06
CPC分类号： G11C16/10
摘要： A method for writing data to non-volatile memory (50) involves alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). After writing, a verify erase (VE) operation and a verify program (VP) operation are performed to determine if multiple cycles are necessary. The method also permits refreshing data in the array without transferring the data onto a data bus for improved security. In one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete. The memory cell structure allows isolation of each bit in the array to avoid adverse effects on neighbor bits.
摘要翻译：一种将数据写入非易失性存储器（50）的方法包括交替地将编程和擦除电压施加到存储器单元的控制门字线。写入包括存储器阵列（56）中的编程和擦除位（30,31，...，32,33）。在写入之后，执行验证擦除（VE）操作和验证程序（VP）操作以确定是否需要多个周期。该方法还允许在阵列中刷新数据而不将数据传输到数据总线上以提高安全性。在一个实施例中，通过向所选字线的漏极选择提供高电压，同时向其它字线的漏极选择提供低电压来写入三晶体管EEPROM。编程和擦除电压以周期的形式施加到所选字线的控制栅极字线，直到写入完成。存储单元结构允许隔离阵列中的每个位，以避免对相邻位的不利影响。

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