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1. 发明授权

US6128224A Method and apparatus for writing an erasable non-volatile memory 有权
标题翻译：用于写入可擦除非易失性存储器的方法和装置
公开(公告)号：US6128224A
公开(公告)日：2000-10-03
申请号：US289699
申请日：1999-04-09
申请人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout , Eric Boulian
发明人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout , Eric Boulian
IPC分类号： G11C16/02 , G11C16/00 , G11C16/10 , G11C16/06
CPC分类号： G11C16/10
摘要： A method for writing data to non-volatile memory (50) involves alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). After writing, a verify erase (VE) operation and a verify program (VP) operation are performed to determine if multiple cycles are necessary. The method also permits refreshing data in the array without transferring the data onto a data bus for improved security. In one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete. The memory cell structure allows isolation of each bit in the array to avoid adverse effects on neighbor bits.
摘要翻译：一种将数据写入非易失性存储器（50）的方法包括交替地将编程和擦除电压施加到存储器单元的控制门字线。写入包括存储器阵列（56）中的编程和擦除位（30,31，...，32,33）。在写入之后，执行验证擦除（VE）操作和验证程序（VP）操作以确定是否需要多个周期。该方法还允许在阵列中刷新数据而不将数据传输到数据总线上以提高安全性。在一个实施例中，通过向所选字线的漏极选择提供高电压，同时向其它字线的漏极选择提供低电压来写入三晶体管EEPROM。编程和擦除电压以周期的形式施加到所选字线的控制栅极字线，直到写入完成。存储单元结构允许隔离阵列中的每个位，以避免对相邻位的不利影响。

2. 发明授权

US6075727A Method and apparatus for writing an erasable non-volatile memory 失效
标题翻译：用于写入可擦除非易失性存储器的方法和装置
公开(公告)号：US6075727A
公开(公告)日：2000-06-13
申请号：US124466
申请日：1998-07-29
申请人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout
发明人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout
IPC分类号： G11C16/10 , G11C16/06 , G11C7/00 , G11C16/04
CPC分类号： G11C16/10
摘要： A method for writing to a bit of a non-volatile memory (50) by alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). Upon completion of the write operation a verify erase (VE) indication and a verify program (VP) indication are provided to a memory controller (58), which then determines if multiple cycles are necessary. The configuration of the memory cell allows isolation of each bit in the memory array to avoid effects of writes to neighbor bits. According to one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete.
摘要翻译：一种通过交替地向存储器单元的控制栅极字线施加编程和擦除电压来写入非易失性存储器（50）的一种方法。写入包括存储器阵列（56）中的编程和擦除位（30,31，...，32,33）。在写入操作完成时，将验证擦除（VE）指示和验证程序（VP）指示提供给存储器控制器（58），存储器控制器（58）然后确定是否需要多个周期。存储器单元的配置允许隔离存储器阵列中的每个位以避免对相邻位的写入的影响。根据一个实施例，通过向所选字线的漏极选择提供高电压，同时向其它字线的漏极选择提供低电压来写入三晶体管EEPROM。编程和擦除电压以周期的形式施加到所选字线的控制栅极字线，直到写入完成。

3. 发明授权

US4860258A Electrically programmable non-volatile memory having sequentially deactivated write circuits 失效
标题翻译：电可编程的非易失性存储器具有顺序取消写入电路
公开(公告)号：US4860258A
公开(公告)日：1989-08-22
申请号：US110274
申请日：1987-10-20
申请人： Serge Fruhauf , Alexis Marquot
发明人： Serge Fruhauf , Alexis Marquot
IPC分类号： G11C17/00 , G11C16/10 , G11C16/26
CPC分类号： G11C16/10 , G11C16/26
摘要： An electrically programmable non-volatile memory includes a matrix of memory cells accessible by rows and columns, write and read circuits which apply potentials, representing the programmed datum or representing the read command, to the rows and columns. The memory also includes a device which controls the interconnection of the write and read circuits with the memory cells, wherein N memory cells are programmed simultaneously, N being greater than 1, each memory cell setting up a current surge when it is programmed at "1". The memory also includes a device for deactivating, one by one, the write circuits corresponding to the N memory cells where there is a change-over from a programming mode to a read mode, and a structure to short-circuit the deactivation device at the change-over to the programming mode.
摘要翻译：电可编程非易失性存储器包括可由行和列访问的存储器单元的矩阵，写入和读取电路，其将表示编程的数据或表示读取命令的电位施加到行和列。存储器还包括控制写入和读取电路与存储器单元的互连的装置，其中N个存储器单元被同时编程，N大于1，每个存储器单元在编程为“1”时设置电流浪涌 “。存储器还包括用于逐个去激活对应于从编程模式到读取模式的转换的N个存储器单元的写入电路的装置，以及用于将停用装置短路的结构切换到编程模式。

4. 发明授权

US6108263A Memory system, method for verifying data stored in a memory system after a write cycle and method for writing to a memory system 有权
标题翻译：存储器系统，用于在写周期之后验证存储在存储器系统中的数据的方法以及用于写入存储器系统的方法
公开(公告)号：US6108263A
公开(公告)日：2000-08-22
申请号：US373305
申请日：1999-08-12
申请人： Philippe Bauser , Alexis Marquot , Craig Swift
发明人： Philippe Bauser , Alexis Marquot , Craig Swift
IPC分类号： G11C16/34 , G11C13/00 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A memory system (20) comprising a memory array (22) having a plurality of memory cells (42) arranged in rows and columns. Each memory cell (42) has a control terminal. A voltage controller (26) provides to the control terminal of a memory cell a first verify voltage signal (Vabse) during a first verify cycle or a second verify voltage signal (Vabsp) during a second verify cycle. The first verify voltage signal (Vabse) having a predetermined voltage level that corresponds substantially to a threshold voltage level of a memory cell in the array in a first state and the second verify voltage signal (Vabsp) having a predetermined voltage level that corresponds substantially to a threshold voltage level of a memory cell in the array in a second state.
摘要翻译：一种存储系统（20），包括具有以行和列排列的多个存储单元（42）的存储器阵列（22）。每个存储器单元（42）具有控制端子。电压控制器（26）在第二验证周期期间在第一验证周期或第二验证电压信号（Vabsp）期间向存储器单元的控制端提供第一验证电压信号（Vabse）。第一验证电压信号（Vabse）具有预定电压电平，其基本上对应于在第一状态下的阵列中的存储器单元的阈值电压电平，以及具有预定电压电平的第二验证电压信号（Vabsp），其基本上对应于处于第二状态的阵列中的存储器单元的阈值电压电平。

5. 发明授权

US4864541A Integrated circuit of the logic circuit type comprising an electrically programmable non-volatile memory 失效
标题翻译：逻辑电路类型的集成电路包括电可编程非易失性存储器
公开(公告)号：US4864541A
公开(公告)日：1989-09-05
申请号：US102554
申请日：1987-09-29
申请人： Alexis Marquot
发明人： Alexis Marquot
IPC分类号： G06F12/14 , G06F21/24 , G06K19/073 , G07F7/10 , G11C16/02 , G11C16/20 , G11C16/22 , G11C17/00
CPC分类号： G11C16/225 , G06K19/0707 , G06K19/0712 , G06K19/073 , G06Q20/341 , G07F7/084 , G07F7/1008 , G11C16/20
摘要： An integrated circuit of the logic circuit type comprises an electrically programmable non-volatile memory formed by a matrix of memory cells of the floating-gate transistor type, with read and write circuits handling the interconnection of these circuits with the memory, the integrated circuit receiving a general power voltage V.sub.CC and a programming voltage V.sub.pp which are different from one another. The circuit can also detect the main power voltage V.sub.CC, sending a signal to prohibit writing in the memory when it is observed that the power voltage V.sub.CC is at zero or in high impedance while thep rogramming voltage is present.
摘要翻译：逻辑电路类型的集成电路包括由浮置晶体管类型的存储单元的矩阵形成的电可编程非易失性存储器，其中读取和写入电路处理这些电路与存储器的互连，集成电路接收一般电源电压VCC和编程电压Vpp彼此不同。该电路还可以检测主电源电压VCC，当存在编程电压时，当观察到电源电压VCC为零或高阻抗时，发送禁止写入存储器的信号。

6. 发明授权

US4827451A Safety device for the programming of an electrically programmable non-volatile memory 失效
标题翻译：用于编程电可编程非易失性存储器的安全装置
公开(公告)号：US4827451A
公开(公告)日：1989-05-02
申请号：US102527
申请日：1987-09-29
申请人： Alexis Marquot , Serge Fruhauf
发明人： Alexis Marquot , Serge Fruhauf
IPC分类号： G06F12/14 , G06F21/06 , G06F21/22 , G06F21/24 , G11C7/24 , G11C16/22 , G11C7/00 , G06F11/00 , G11C8/00
CPC分类号： G11C7/24 , G11C16/22
摘要： In a memory consisting of a matrix of memory cells, each of which is accessible by rows and columns and is connected to write and read circuits which are used, respectively, to programme them in two states, "1" or "0", depending on the input data, and to read the programmed state, the memory cells being of the type that require a programming current in order to be programmed in a first state or "1" and require no current to be programmed in a second state or "0", the safety device consists of a simulation circuit activated by data corresponding to a "0" programming operation and delivering a current identical to that of a memory cell in the "1" programming condition.
摘要翻译：在由存储器单元矩阵组成的存储器中，每个存储器单元可通过行和列访问，并且分别连接到写入和读取电路，以分别在两种状态“1”或“0”中编程，这取决于并且为了读取编程状态，存储器单元是需要编程电流的类型，以便被编程在第一状态或“1”，并且不需要在第二状态下编程电流或“ 0“时，安全装置包括由对应于”0“编程操作的数据激活的模拟电路，并且传送与”1“编程条件下的存储单元相同的电流。

7. 发明授权

US06636402B1 High voltage protection circuit 有权
标题翻译：高压保护电路
公开(公告)号：US06636402B1
公开(公告)日：2003-10-21
申请号：US09610786
申请日：2000-07-06
申请人： Alexis Marquot , Philippe Bauser
发明人： Alexis Marquot , Philippe Bauser
IPC分类号： H02H320
CPC分类号： H01L27/0255 , H01L27/0266
摘要： A high voltage protection circuit (20) in a non-volatile memory includes a first transistor (22) and a second transistor (24) each formed in their own separate wells. A high voltage supply (Vhv) is provided at the drain of the second transistor (24). The source (40) of second transistor (24) is connected to the drain of first transistor (22) and to well (32), and the gate of the second transistor (24) is connected to Vdd, the main power supply to the chip. By forming the transistors in their own separate wells with the source of the second transistor (24) connected to its own well, breakdown of the circuit is governed by the sum of BVdss of the first transistor (22) and a gate induced breakdown (BVind) of the second transistor (24). With this circuit use of even a low Vdd (e.g.
摘要翻译：非易失性存储器中的高压保护电路（20）包括分别形成在它们各自的单独的阱中的第一晶体管（22）和第二晶体管（24）。在第二晶体管（24）的漏极处提供高电压源（Vhv）。第二晶体管（24）的源极（40）连接到第一晶体管（22）和阱（32）的漏极，并且第二晶体管（24）的栅极连接到Vdd，主电源芯片。通过在第二晶体管（24）的源极连接到其自己的阱上，在它们自己的单独的阱中形成晶体管，电路的击穿由第一晶体管（22）的BVdss和栅极引起的击穿（BVind ）的第二晶体管（24）。利用该电路，即使在第二晶体管（24）的栅极上使用低Vdd（例如<3V）也足以防止不希望的暴露于Vhs或防止泄漏，从而不需要产生更高的间隔电压，路由到电路。

8. 发明授权

US5978262A Circuit and method of latching a bit line in a non-volatile memory 失效
标题翻译：在非易失性存储器中锁存位线的电路和方法
公开(公告)号：US5978262A
公开(公告)日：1999-11-02
申请号：US9290
申请日：1998-01-20
申请人： Alexis Marquot , Jean-Claude Tarbouriech , Paul Dechamps
发明人： Alexis Marquot , Jean-Claude Tarbouriech , Paul Dechamps
IPC分类号： G11C16/10 , G11C16/12 , G11C16/14
CPC分类号： G11C16/10 , G11C16/12
摘要： A portable data carrier (10) embodies an integrated circuit (12) with an EEPROM (24). The EEPROM has a number of rows of memory cells (32, 38, 44) each having outputs respectively coupled to bit lines (50, 54, 56), and control inputs coupled to a common control line (132). The bit lines each include a latch (60, 62, 64) that is set to provide a programming voltage (VPP) during write mode. The bit lines have serial switches (78, 80, 82) that break continuity when writing to the latches. The bit line latches are made transparent to the bit lines during read mode. The common control line is coupled through a programming transistor (130) to an erase line (72). The erase line must be driven to a programming voltage during erase mode. The erase line uses one of the bit line latches to provide its programming voltage.
摘要翻译：便携式数据载体（10）体现了具有EEPROM（24）的集成电路（12）。 EEPROM具有多行存储单元（32,38,44），每行存储单元具有分别耦合到位线（50,54,56）的输出和耦合到公共控制线（132）的控制输入。位线各自包括被设置为在写入模式期间提供编程电压（VPP）的锁存器（60,62,64）。位线具有串行开关（78,80,82），可在写入锁存器时断开连续性。在读取模式期间，位线锁存器对位线是透明的。公共控制线通过编程晶体管（130）耦合到擦除线（72）。在擦除模式下，必须将擦除线驱动到编程电压。擦除线使用位线锁存器之一来提供其编程电压。

9. 发明授权

US5886926A Circuit and method of measuring the negative threshold voltage of a non-volatile memory cell 失效
标题翻译：测量非易失性存储单元的负阈值电压的电路和方法
公开(公告)号：US5886926A
公开(公告)日：1999-03-23
申请号：US10042
申请日：1998-01-20
申请人： Alexis Marquot
发明人： Alexis Marquot
IPC分类号： G11C16/06 , G11C16/34 , G11C29/12 , G11C29/50
CPC分类号： G11C29/50004 , G11C16/34 , G11C29/50 , G06F2201/81 , G11C16/04
摘要： A portable data carrier (10) embodies an integrated circuit (12) with an EEPROM (24). The EEPROM has a number of rows of memory cells (32, 38) each having outputs respectively coupled to bit lines (50, 54). The EEPROM cells have a common array ground node (56). A pull-up transistor (74) is coupled to the common array ground node for developing a first positive voltage on the common array ground node which in turn develops a second positive voltage on the output of one of the memory cells corresponding to a negative threshold voltage of the memory cells. A sensing circuit (88) is coupled to one of the bit lines for detecting the level of the second positive voltage and thus determining the negative threshold voltage of the memory cell.
摘要翻译：便携式数据载体（10）体现了具有EEPROM（24）的集成电路（12）。 EEPROM具有多行存储单元（32,38），每行具有分别耦合到位线（50,54）的输出。 EEPROM单元具有公共阵列接地节点（56）。上拉晶体管（74）耦合到公共阵列接地节点，用于在公共阵列接地节点上形成第一正电压，其又在对应于负阈值的一个存储器单元的输出上产生第二正电压存储单元的电压。感测电路（88）耦合到位线之一，用于检测第二正电压的电平，从而确定存储单元的负阈值电压。

10. 发明授权

US4837744A Integrated circuit of the logic circuit type comprising an electrically programmable non-volatile memory 失效
标题翻译：逻辑电路类型的集成电路包括电可编程非易失性存储器
公开(公告)号：US4837744A
公开(公告)日：1989-06-06
申请号：US116692
申请日：1987-11-04
申请人： Alexis Marquot
发明人： Alexis Marquot
IPC分类号： G11C17/00 , G07F7/10 , G11C16/02 , G11C16/22 , G11C16/32
CPC分类号： G07F7/1008 , G06Q20/341 , G07F7/084 , G11C16/22 , G11C16/32
摘要： An integrated circuit of the logic circuit type includes a matrix of memory cells of the floating-gate transistor type, write and read circuits and circuitry to handle the interconnection of these circuits with the memory. The integrated circuit receives a general supply voltage Vcc, a programming voltage Vpp and an external clock signal divided into two complementary clock signals. The clock signals acts on, among others, the functioning of the write circuits. The integrated circuit further includes a circuit to detect the presence of internal clock signals. The circuit sends a signal prohibiting write operations in the memory when it detects the absence of one of the internal clock signals.
摘要翻译：逻辑电路类型的集成电路包括浮置晶体管类型的存储器单元的矩阵，写入和读取电路以及用于处理这些电路与存储器的互连的电路。集成电路接收一般电源电压Vcc，编程电压Vpp和被分成两个互补时钟信号的外部时钟信号。时钟信号尤其影响写入电路的功能。集成电路还包括用于检测内部时钟信号的存在的电路。当电路检测到不存在其中一个内部时钟信号时，电路发送禁止写入操作的信号。

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