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1. 发明授权

US06650163B1 Clock generator for integrated circuit 有权
标题翻译：时钟发生器用于集成电路
公开(公告)号：US06650163B1
公开(公告)日：2003-11-18
申请号：US10216618
申请日：2002-08-08
申请人： Jeffrey L. Burns , Alan James Drake , Uttam Shyamalindu Ghoshal , Kevin John Nowka
发明人： Jeffrey L. Burns , Alan James Drake , Uttam Shyamalindu Ghoshal , Kevin John Nowka
IPC分类号： H03K300
CPC分类号： H03B5/1212 , H03B5/1228 , H03K3/354
摘要： A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator's inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.
摘要翻译：一种包括时钟发生器的系统和集成电路（芯片），其包括片上电感器并且使用负载的固有电容来产生正弦时钟信号。电感连接在电流源和反相开关之间。开关的输出是基本上正弦信号，其直接连接到时钟驱动电路的至少一部分而没有中间缓冲。在优选实施例中，时钟发生器是双相设计，其包括一对交叉耦合MOSFET，一对固态片上电感器和电流源。每个片上电感器连接在MOSFET之一的电流源和漏极之间。时钟发生器的输出被直接提供给芯片上至少一部分时钟驱动电路的时钟输入。在该实施例中，时钟发生器输出信号的频率主要由电感元件的电感和时钟驱动电路的电容决定。该设计消除了在时钟发生器本身中并入不同的电容器元件并产生时钟发生器的需要，其中大部分功率在发电机的感应元件和负载的电容元件之间振荡，从而减少由当前来源。

2. 发明授权

US07443195B2 Method of transparently reducing power consumption of a high-speed communication link 失效
标题翻译：透明地降低高速通信链路的功耗的方法
公开(公告)号：US07443195B2
公开(公告)日：2008-10-28
申请号：US10773427
申请日：2004-02-09
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H03K19/0175 , G05F1/10
CPC分类号： H03K19/0008
摘要： A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.
摘要翻译：提供一种在保持性能特性的同时降低功耗并避免嵌入在SOC中的高速通信链路的昂贵的过度设计的方法。该方法包括以降低的电压合成通信链路，以确定和隔离与非电源电压关键的电路相关的电源电压关键的电路。电源电压关键电路包含不降低电压而不降低通信链路性能特性的组件。使用非降低电压来驱动电源电压关键电路，同时使用降低的电压来驱动非电源电压关键电路。使用嵌入在通信链路中的电压调节器来产生降低的电压。

3. 发明授权

US6035390A Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation 失效
标题翻译：用于与执行算术或逻辑运算同时产生和逻辑组合小于（LT），大于（GT）和等于（EQ））条件码位的方法和装置
公开(公告)号：US6035390A
公开(公告)日：2000-03-07
申请号：US5471
申请日：1998-01-12
申请人： Jeffrey L. Burns , Sang Hoo Dhong , Kevin John Nowka , Joel Abraham Silberman
发明人： Jeffrey L. Burns , Sang Hoo Dhong , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G06F9/38 , G06F7/48 , G06F9/302 , G06F9/305 , G06F9/32 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/48 , G06F9/30094
摘要： A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that determines less than, greater than, and equal to condition code bits associated with the instruction concurrently with execution of the instruction by the execution unit. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits.
摘要翻译：处理器至少包括一个执行单元，该执行单元通过使用一个或多个操作数和条件代码逻辑执行指令所指示的操作来执行指令，所述操作数和条件代码逻辑确定小于，大于和等于与执行同时执行的指令相关联的条件代码位的执行单元的指令。在一个实施例中，条件码逻辑包括单个计算阶段，其接收第一和第二操作数中的比特位置的各个比特值作为输入，并逻辑地组合各个比特值。对于每个位位置，单个计算级输出传播，产生和去除共同指示小于，大于和等于条件码位的值的信号。耦合到计算阶段的一个或多个合并阶段然后将传播，生成和终止信号合并到设置条件码位的输出信号中。

4. 发明授权

US06812739B2 Method of transparently reducing power consumption of a high-speed communication link 失效
公开(公告)号：US06812739B2
公开(公告)日：2004-11-02
申请号：US10255471
申请日：2002-09-26
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H03K190175
CPC分类号： H03K19/0008
摘要： A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

5. 发明授权

US06724221B2 Circuitry having exclusive-OR and latch function, and method therefor 失效
标题翻译：具有异或和锁存功能的电路及其方法
公开(公告)号：US06724221B2
公开(公告)日：2004-04-20
申请号：US10112513
申请日：2002-03-28
申请人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Kevin John Nowka , Li Shi
发明人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Kevin John Nowka , Li Shi
IPC分类号： H03K1921
CPC分类号： H03K19/215
摘要： In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timing circuitry portions, each operable to receive at least one timing signal, coupled to the respective memory nodes. The logic circuitry includes first and second logic circuitry portions, each of which is operable to receive at least first and second data signals. Each of the logic circuitry portions is coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions.
摘要翻译：在本发明的一种形式中，具有异或和锁存功能的电路包括定时电路和逻辑电路。电路包括具有用于存储状态及其补码的第一和第二存储器节点的存储器，以及第一和第二定时电路部分，每个定时电路部分可操作以接收耦合到相应存储器节点的至少一个定时信号。逻辑电路包括第一和第二逻辑电路部分，每个逻辑电路部分可操作以接收至少第一和第二数据信号。每个逻辑电路部分与相应的第一和第二定时电路部分之一的条件导电路径串联耦合。

6. 发明授权

US07269397B2 Method and apparatus for measuring communications link quality 失效
标题翻译：测量通信链路质量的方法和装置
公开(公告)号：US07269397B2
公开(公告)日：2007-09-11
申请号：US11424209
申请日：2006-06-14
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
IPC分类号： H04B17/02
CPC分类号： H04B17/20
摘要： A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
摘要翻译：用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率（BER）的难度的精确的片上估计。连接到来自时钟/数据恢复（CDR）电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。低频抖动测量用于校正可能包含错误的高频抖动测量。校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正，或者可以使用低频抖动测量的值来选择两个或更多个校正因子，然后将其应用于高频抖动抖动测量。

7. 发明授权

US08271055B2 Interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage 失效
标题翻译：接口收发器功率管理方法和装置，包括受控电路复杂度和电源电压
公开(公告)号：US08271055B2
公开(公告)日：2012-09-18
申请号：US10302494
申请日：2002-11-21
申请人： Juan-Antonio Carballo , Jeffrey L. Burns
发明人： Juan-Antonio Carballo , Jeffrey L. Burns
IPC分类号： H04M1/00 , H04B1/38 , H01Q11/12 , H04B1/04
CPC分类号： H04W52/04
摘要： An interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage reduces power consumption when interface conditions will support a transceiver having reduced complexity. The power supply voltage of the reduced complexity logic is then reduced if the lowered complexity will support a lower power supply voltage. The reduced complexity in combination with a reduced power supply voltage decreases power consumption to a greater degree than reducing transceiver complexity alone.The complexity of processing blocks within the receiver and/or transmitter are adjusted in conformity with one or more selection signals and an operating voltage level is selected in accordance with the requirements of the reduced complexity circuit. An interface quality measurement circuit may provide the selection signal, so that the transceiver complexity is adjusted in response to measured interface conditions or an external pin or register bit may be coupled to a select input.
摘要翻译：包括受控电路复杂度和电源电压的接口收发器功率管理方法和装置在接口条件将支持具有降低的复杂度的收发器时降低功耗。如果降低的复杂度将支持较低的电源电压，则降低的复杂度逻辑的电源电压将被降低。与降低的电源电压相结合的降低的复杂性比仅降低收发器复杂性更大程度地降低功耗。根据一个或多个选择信号调整接收器和/或发射器内的处理块的复杂度，并且根据降低的复杂度电路的要求来选择工作电压电平。接口质量测量电路可以提供选择信号，使得响应于测量的接口条件来调整收发器复杂度，或者外部引脚或寄存器位可以耦合到选择输入。

8. 发明授权

US07133654B2 Method and apparatus for measuring communications link quality 失效
标题翻译：测量通信链路质量的方法和装置
公开(公告)号：US07133654B2
公开(公告)日：2006-11-07
申请号：US10636992
申请日：2003-08-07
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Ivan Vo
IPC分类号： H04B17/02
CPC分类号： H04B17/20
摘要： A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
摘要翻译：用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率（BER）的难度的精确的片上估计。连接到来自时钟/数据恢复（CDR）电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。低频抖动测量用于校正可能包含错误的高频抖动测量。校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正，或者可以使用低频抖动测量的值来选择两个或更多个校正因子，然后将其应用于高频抖动抖动测量。

9. 发明授权

US06791361B2 Technique for mitigating gate leakage during a sleep state 失效
标题翻译：在睡眠状态下减轻门漏电的技术
公开(公告)号：US06791361B2
公开(公告)日：2004-09-14
申请号：US10319002
申请日：2002-12-12
申请人： Elad Alon , Jeffrey L. Burns , Kevin J. Nowka , Rahul M. Rao
发明人： Elad Alon , Jeffrey L. Burns , Kevin J. Nowka , Rahul M. Rao
IPC分类号： H03K19003
CPC分类号： H03K19/0016
摘要： A method and circuit for mitigating gate leakage during a sleep state. An input pattern may be applied to one or more of a plurality of devices in a circuit, e.g., static circuit, dynamic circuit, during a sleep state. In response to the application of the input pattern, a majority of the devices in the circuit may have a substantially identical voltage at each of its terminals, i.e., the source, gate and drain terminal, thereby mitigating gate leakage.
摘要翻译：一种在睡眠状态下减轻门漏电的方法和电路。在休眠状态期间，可以将输入模式应用于电路中的多个设备中的一个或多个，例如静态电路，动态电路。响应于输入图案的应用，电路中的大多数器件可以在其每个端子，即源极，栅极和漏极端子处具有基本相同的电压，从而减轻栅极泄漏。

10. 发明授权

US06621358B2 Differential voltage controlled oscillator, and method therefor 失效
标题翻译：差分压控振荡器及其方法
公开(公告)号：US06621358B2
公开(公告)日：2003-09-16
申请号：US10015384
申请日：2001-12-17
申请人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Ivan Vo
发明人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Ivan Vo
IPC分类号： H03B500
CPC分类号： H03K5/133 , H03K3/0322 , H03K2005/00208 , H03K2005/00234
摘要： In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.
摘要翻译：在第一形式中，压控振荡器包括以环形连接的延迟单元，以及连接到选择性地旁路各组延迟单元的控制元件。延迟单元可操作以接收相应的差分输入并产生反相输出。控制元件可操作以接收相应的差分输入并产生具有可变延迟的非反相输出。响应于各个差分控制电压，控制元件延迟是可变的。

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