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1. 发明申请

US20080125063A1 DIGITAL TRANSMISSION CIRCUIT AND INTERFACE PROVIDING SELECTABLE POWER CONSUMPTION VIA MULTIPLE WEIGHTED DRIVER SLICES 有权
标题翻译：数字传输电路和接口，通过多个加权驱动器提供可选择的功耗
公开(公告)号：US20080125063A1
公开(公告)日：2008-05-29
申请号：US12024448
申请日：2008-02-01
申请人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H01Q11/12
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译：数字传输电路和接口通过多个加权驱动器片提供可选择的功耗，提高接口的灵活性，同时在可能的同时降低发射机功耗，面积和复杂性。级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。

2. 发明申请

US20080125062A1 DIGITAL TRANSMISSION CIRCUIT AND METHOD PROVIDING SELECTABLE POWER CONSUMPTION VIA MULTIPLE WEIGHTED DRIVER SLICES 有权
标题翻译：数字传输电路和通过多重加权驱动器提供可选择的功耗的方法
公开(公告)号：US20080125062A1
公开(公告)日：2008-05-29
申请号：US12015458
申请日：2008-01-16
申请人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H01Q11/12
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译：通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低功耗。级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。

3. 发明申请

US20060172715A1 Digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices 有权
标题翻译：数字传输电路和方法通过多个加权驱动器片提供可选择的功耗
公开(公告)号：US20060172715A1
公开(公告)日：2006-08-03
申请号：US11050019
申请日：2005-02-03
申请人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Kevin Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H04B1/04 , H01Q11/12 , H03F3/68
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译：通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低了发射机功耗，面积和复杂度。级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。

4. 发明授权

US06977528B2 Event driven dynamic logic for reducing power consumption 有权
标题翻译：事件驱动的动态逻辑，用于降低功耗
公开(公告)号：US06977528B2
公开(公告)日：2005-12-20
申请号：US10325594
申请日：2002-12-20
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： H03K3/012 , H03K19/00 , H03K19/096
CPC分类号： H03K3/012 , H03K19/0016 , H03K19/0963
摘要： Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.
摘要翻译：描述了方法和电路，用于当时钟信号不会在逻辑电路内产生期望的状态变化时，例如在输入，中间节点处，通过阻止时钟信号转换到逻辑电路来减少数字逻辑电路内的功耗，输出或组合。作为示例，如果要接收时钟信号转换，如果给定的一组逻辑输入不会导致状态的输出改变，则输入时钟被阻塞。作为进一步的示例，如果输入信号与输出信号匹配，则输入时钟在数据触发器中被阻塞，使得接收到时钟转换将不会在锁存输出中产生期望的状态变化。本发明可以用于创建较低功率的组合和/或顺序逻辑电路级，所述低功率组合和/或顺序的逻辑电路级经历栅极电容的不经济的充电和放电。

5. 发明授权

US06972598B2 Methods and arrangements for an enhanced scanable latch circuit 失效
公开(公告)号：US06972598B2
公开(公告)日：2005-12-06
申请号：US10730958
申请日：2003-12-09
申请人： Seung-Moon Yoo
发明人： Seung-Moon Yoo
IPC分类号： G01R31/3185 , H03K19/096 , H03K19/20
CPC分类号： G01R31/318575
摘要： Methods, and arrangements to enhance speed and reduce power consumption in a scanable latch circuit are disclosed. Embodiments include a wired-or circuit to facilitate independent paths for scan data and normal input data through the scanable latch circuit. In particular, to reduce delays related to gates between the input pin for the system clock and a normal input gate, dual, substantially independent paths are implemented: a scan path and a normal input path. Embodiments coordinate transmission of data from a normal input gate and a scan input gate to an output latch, a scan out pin, and/or combinational logic by incorporating buffers that isolate a wired-or node from either the scan input gate, the normal input gate, or both with a high impedance.

6. 发明申请

US20050122136A1 Methods and arrangements for an enhanced scanable latch circuit 失效
标题翻译：增强型可扫描锁存电路的方法和布置
公开(公告)号：US20050122136A1
公开(公告)日：2005-06-09
申请号：US10730958
申请日：2003-12-09
申请人： Seung-Moon Yoo
发明人： Seung-Moon Yoo
IPC分类号： G01R31/3185 , H03K19/096 , H03K19/20
CPC分类号： G01R31/318575
摘要： Methods, and arrangements to enhance speed and reduce power consumption in a scanable latch circuit are disclosed. Embodiments include a wired-or circuit to facilitate independent paths for scan data and normal input data through the scanable latch circuit. In particular, to reduce delays related to gates between the input pin for the system clock and a normal input gate, dual, substantially independent paths are implemented: a scan path and a normal input path. Embodiments coordinate transmission of data from a normal input gate and a scan input gate to an output latch, a scan out pin, and/or combinational logic by incorporating buffers that isolate a wired-or node from either the scan input gate, the normal input gate, or both with a high impedance.
摘要翻译：公开了一种在可扫描锁存电路中提高速度并降低功耗的方法和装置。实施例包括有助于扫描数据和通过可扫描锁存电路的正常输入数据的独立路径的有线或电路。特别地，为了减少与用于系统时钟的输入引脚和普通输入门之间的门相关的延迟，实现了两个基本独立的路径：扫描路径和正常输入路径。实施例通过结合将有线或节点与扫描输入门，正常输入端隔离的缓冲器，将数据从普通输入门和扫描输入门传输到输出锁存器，扫描输出引脚和/或组合逻辑门或两者具有高阻抗。

7. 发明授权

US06900690B2 Low-power high-performance integrated circuit and related methods 有权
公开(公告)号：US06900690B2
公开(公告)日：2005-05-31
申请号：US10729726
申请日：2003-12-05
申请人： Sung-Mo Kang , Seung-Moon Yoo
发明人： Sung-Mo Kang , Seung-Moon Yoo
IPC分类号： H03K3/012 , H03K19/00 , G05F1/10
CPC分类号： H03K3/012 , H03K19/0016
摘要： An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

8. 发明授权

US06812739B2 Method of transparently reducing power consumption of a high-speed communication link 失效
公开(公告)号：US06812739B2
公开(公告)日：2004-11-02
申请号：US10255471
申请日：2002-09-26
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H03K190175
CPC分类号： H03K19/0008
摘要： A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

9. 发明授权

US5845108A Semiconductor memory device using asynchronous signal 失效
标题翻译：半导体存储器件采用异步信号
公开(公告)号：US5845108A
公开(公告)日：1998-12-01
申请号：US781953
申请日：1996-12-19
申请人： Seung-Moon Yoo , Ejaz Ul Haq
发明人： Seung-Moon Yoo , Ejaz Ul Haq
IPC分类号： G11C11/407 , G11C5/06 , G11C7/00 , G11C7/22 , G06F1/04
CPC分类号： G11C7/22 , G11C5/066
摘要： A semiconductor memory device such as a DRAM has an internal oscillator to provide a periodic clock signal. During a read operation, output data is generated synchronized to the internal clock signal, and an external control signal is provided also synchronized to the internal clock signal. A requesting device utilizes the external control signal for fetching data from the memory device at high speed with improved setup and hold time. The control signal output is active only during a read operation, thereby reducing power consumption. Additionally, a common line is used for receiving address, instructions, and data. This drastically reduces the number of pins for interfacing to a memory device.
摘要翻译：诸如DRAM的半导体存储器件具有内部振荡器以提供周期性的时钟信号。在读取操作期间，产生与内部时钟信号同步的输出数据，并且提供外部控制信号也与内部时钟信号同步。请求设备利用外部控制信号，以高速提取存储设备中的数据，具有改进的建立和保持时间。控制信号输出仅在读取操作期间有效，从而降低功耗。另外，公共线路用于接收地址，指令和数据。这大大减少了与存储器件接口的引脚数量。

10. 发明授权

US5640362A Lead frame clock distribution for integrated circuit memory devices 失效
标题翻译：集成电路存储器件的引线框时钟分配
公开(公告)号：US5640362A
公开(公告)日：1997-06-17
申请号：US701702
申请日：1996-08-22
申请人： Seung-moon Yoo
发明人： Seung-moon Yoo
IPC分类号： G11C11/413 , G11C5/00 , G11C7/10 , G11C7/22 , G11C11/34 , G11C11/401 , G11C11/407 , G11C11/41 , H01L21/8242 , H01L27/108 , G11C13/00
CPC分类号： G11C5/06 , G11C5/04 , G11C7/1072 , G11C7/22
摘要： Clock pads are distributed over an integrated circuit memory device and electrically connected to a lead frame to synchronously provide an external clock signal to the clock pads. Accordingly, an internal clock signal is generated throughout the integrated circuit memory device by distributing an external clock signal using a lead frame and pads. Internal circuitry for generating and synchronizing an internal clock from an external clock is thereby not required. When the integrated circuit memory device includes multiple memory array banks, the clock pads may be located in a row of input/output pads adjacent a memory array bank or between pairs of memory array banks.
摘要翻译：时钟焊盘分布在集成电路存储器件上并电连接到引线框架，以同步地向时钟焊盘提供外部时钟信号。因此，通过使用引线框和焊盘分配外部时钟信号，在整个集成电路存储器件中产生内部时钟信号。因此不需要用于从外部时钟产生和同步内部时钟的内部电路。当集成电路存储器件包括多个存储器阵列组时，时钟焊盘可以位于与存储器阵列组相邻或存储阵列组对之间的输入/输出焊盘行中。

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