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1. 发明申请

US20100100200A1 DISCOVERY OF CONNECTIONS UTILIZING A CONTROL BUS 有权
标题翻译：发现使用控制总线的连接
公开(公告)号：US20100100200A1
公开(公告)日：2010-04-22
申请号：US12577707
申请日：2009-10-12
申请人： Jason Seung-Min Kim , Inyeol Lee , Shrikant Ranade , Daeyun Shim
发明人： Jason Seung-Min Kim , Inyeol Lee , Shrikant Ranade , Daeyun Shim
IPC分类号： G05B11/01
CPC分类号： G06F13/4022 , G06F13/4081
摘要： Discovery of connections utilizing a control bus. An embodiment of a method includes detecting a transition of a control bus from a high state to a low state by a source device, the source device being configured to be coupled with a sink device via an interface, the interface including the control bus, the source device including a pullup device and the sink device including a pulldown device;pulsing the control bus to a high state at the source device; and upon detecting by the source device that the control bus remains in the high state ceasing the pulsing of the control bus to the high state, and transitioning the source device from a disconnected state to a connected state.
摘要翻译：发现使用控制总线的连接。一种方法的实施例包括：通过源设备检测控制总线从高状态到低状态的转换，源设备被配置为经由接口与宿设备耦合，所述接口包括控制总线，源装置，其包括上拉装置，并且所述信宿装置包括下拉装置;将所述控制总线脉冲到所述源装置处的高状态; 并且当源设备检测到控制总线保持在高状态时，停止控制总线的脉冲到高状态，并且将源设备从断开状态转换到连接状态。

2. 发明授权

US08275914B2 Discovery of connections utilizing a control bus 有权
标题翻译：发现使用控制总线的连接
公开(公告)号：US08275914B2
公开(公告)日：2012-09-25
申请号：US12577707
申请日：2009-10-12
申请人： Jason Seung-Min Kim , Inyeol Lee , Shrikant Ranade , Daeyun Shim
发明人： Jason Seung-Min Kim , Inyeol Lee , Shrikant Ranade , Daeyun Shim
IPC分类号： G06F3/00
CPC分类号： G06F13/4022 , G06F13/4081
摘要： Discovery of connections utilizing a control bus. An embodiment of a method includes detecting a transition of a control bus from a high state to a low state by a source device, the source device being configured to be coupled with a sink device via an interface, the interface including the control bus, the source device including a pullup device and the sink device including a pulldown device; pulsing the control bus to a high state at the source device; and upon detecting by the source device that the control bus remains in the high state ceasing the pulsing of the control bus to the high state, and transitioning the source device from a disconnected state to a connected state.
摘要翻译：发现使用控制总线的连接。一种方法的实施例包括：通过源设备检测控制总线从高状态到低状态的转换，源设备被配置为经由接口与宿设备耦合，所述接口包括控制总线，源设备，包括上拉设备和宿设备，其包括下拉设备; 将控制总线脉冲到源设备处于高状态; 并且当源设备检测到控制总线保持在高状态时，停止控制总线的脉冲到高状态，并且将源设备从断开状态转换到连接状态。

3. 发明申请

US20100104029A1 INDEPENDENT LINK(S) OVER DIFFERENTIAL PAIRS USING COMMON-MODE SIGNALING 审中-公开
标题翻译：使用通用模式信号的独立链路的独立链路
公开(公告)号：US20100104029A1
公开(公告)日：2010-04-29
申请号：US12603176
申请日：2009-10-21
申请人： Inyeol Lee , Daeyun Shim , Ook Kim , Gyudong Kim
发明人： Inyeol Lee , Daeyun Shim , Ook Kim , Gyudong Kim
IPC分类号： H04L27/00 , H04L25/00 , H04B3/00
CPC分类号： H04L5/1423 , H04B3/50 , H04L5/20 , H04L25/0272 , H04L25/0276 , H04L25/028 , H04L25/061
摘要： Methods and apparatuses for using single-ended common mode signaling, additional data can be transferred in backward, forward, and/or both directions over an existing differential pair connection without adding extra wire.
摘要翻译：使用单端共模信令的方法和装置，可以通过现有的差分对连接在后向，前向和/或两个方向上传送附加数据，而不增加额外的电线。

4. 发明授权

US06809567B1 System and method for multiple-phase clock generation 有权
标题翻译：用于多相时钟生成的系统和方法
公开(公告)号：US06809567B1
公开(公告)日：2004-10-26
申请号：US09989645
申请日：2001-11-20
申请人： Ook Kim , Hung Sung Li , Inyeol Lee , Gyudong Kim , Yongman Lee
发明人： Ook Kim , Hung Sung Li , Inyeol Lee , Gyudong Kim , Yongman Lee
IPC分类号： H03L700
CPC分类号： H03K23/542 , G06F1/06 , H03K5/15013 , H03L7/0891 , H03L7/0995
摘要： A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (“VCO”) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e.g., a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.
摘要翻译：公开了一种用于多相时钟产生的系统和方法。在一个实施例中，多级压控振荡器（“VCO”）将多个时钟相位发送到产生期望数量的时钟相位输出的时钟分频器电路。该实施例中的时钟分频器电路包括一个状态机，例如修改的约翰逊计数器，其提供多个划分的下降时钟相位，每个分频下降沿连接到单独的修改的移位寄存器。每个修改的移位寄存器包含D型触发器，每个D型触发器提供单独的时钟相位输出。在一个实施例中，多相时钟的时钟相位输出的数量是VCO时钟相位数乘以修改的约翰逊计数器中期望状态数量的函数。

5. 发明授权

US06717478B1 Multi-phase voltage controlled oscillator (VCO) with common mode control 有权
标题翻译：具有共模控制的多相压控振荡器（VCO）
公开(公告)号：US06717478B1
公开(公告)日：2004-04-06
申请号：US09989587
申请日：2001-11-20
申请人： Ook Kim , Hung Sung Li , Inyeol Lee , Gyudong Kim , Yongman Lee
发明人： Ook Kim , Hung Sung Li , Inyeol Lee , Gyudong Kim , Yongman Lee
IPC分类号： H03B2700
CPC分类号： H03L7/0995 , H03B5/24 , H03B27/00 , H03L7/0891
摘要： A voltage controlled oscillator (“VCO”) circuit capable of generating signals with reduced jitter and/or low-phase noise is provided. One embodiment provides a plurality of cascaded VCO cells, where each VCO cell can include a source coupled differential pair, a bias transistor connected to the differential pair for biasing the differential pair, a resistive load pair connected to the differential pair, and a voltage controlled capacitor pair or varactor pair connected to the differential pair. The varactors provide control over the frequency of the oscillations produced by the VCO circuit in combination with a control voltage. A phase frequency detector combined with a charge pump and loop filter provide the control voltage.
摘要翻译：提供了能够产生具有降低的抖动和/或低相位噪声的信号的压控振荡器（“VCO”）电路。一个实施例提供多个级联VCO单元，其中每个VCO单元可以包括源极耦合差分对，连接到差分对的偏置晶体管，用于偏置差分对，连接到差分对的电阻负载对，以及电压控制电容器对或变容二极管对连接到差分对。变容二极管提供对由VCO电路产生的振荡频率与控制电压的组合的控制。与电荷泵和环路滤波器组合的相位检波器提供控制电压。

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