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1. 发明授权

US06567303B1 Charge injection 有权
标题翻译：电荷注入
公开(公告)号：US06567303B1
公开(公告)日：2003-05-20
申请号：US10050483
申请日：2002-01-16
申请人： Darlene G. Hamilton , Janet S. Y. Wang , Narbeh Derhacobian , Tim Thurgate , Michael K. Han
发明人： Darlene G. Hamilton , Janet S. Y. Wang , Narbeh Derhacobian , Tim Thurgate , Michael K. Han
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445
摘要： A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.
摘要翻译：提供了一种用于以基本上高的delta VT对双位存储器单元的存储器阵列的第一和第二位进行编程的系统和方法。基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。在基本上较高的增量VT下，存储器单元的第一位的编程使得第二位由于较短的通道长度而更硬更快地编程。因此，本发明在第一和第二位的编程期间采用选择的栅极和漏极电压以及编程脉冲宽度，以确保受控的第一位VT并减慢第二位的编程。此外，所选择的编程参数保持编程时间短而不降低电荷损耗。

2. 发明授权

US06331952B1 Positive gate erasure for non-volatile memory cells 有权
标题翻译：非易失性存储单元的正门擦除
公开(公告)号：US06331952B1
公开(公告)日：2001-12-18
申请号：US09697810
申请日：2000-10-26
申请人： Janet S. Y. Wang , Narbeh Derhacobian , Ravi S. Sunkavalli
发明人： Janet S. Y. Wang , Narbeh Derhacobian , Ravi S. Sunkavalli
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C16/14
摘要： A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes simultaneously applying a first positive voltage across the gate and a second positive voltage to the first region, wherein the second positive voltage is greater than the first positive voltage.
摘要翻译：一种擦除存储单元的方法，该存储单元包括第一区域和第二区域以及通道之间的通道，以及包含第一电荷量的电荷捕获区域。该方法包括同时对栅极施加第一正电压，向第一区施加第二正电压，其中第二正电压大于第一正电压。

3. 发明授权

US06590811B1 Higher program VT and faster programming rates based on improved erase methods 失效
公开(公告)号：US06590811B1
公开(公告)日：2003-07-08
申请号：US10173262
申请日：2002-06-17
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S. Y. Wang , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S. Y. Wang , Kulachet Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C29/50004
摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

4. 发明授权

US06269023B1 Method of programming a non-volatile memory cell using a current limiter 有权
标题翻译：使用限流器对非易失性存储单元进行编程的方法
公开(公告)号：US06269023B1
公开(公告)日：2001-07-31
申请号：US09694729
申请日：2000-10-23
申请人： Narbeh Derhacobian , Janet S. Y. Wang , Daniel Sobek , Sameer S. Haddad
发明人： Narbeh Derhacobian , Janet S. Y. Wang , Daniel Sobek , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475
摘要： A memory cell that includes a substrate that has a first region and a second region with a channel therebetween, wherein the first region generates hot carriers. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge. A current limiter that limits the number of the generated hot carriers that can flow into the channel, wherein the current limiter does not control the voltage of the second region.
摘要翻译：一种存储单元，包括具有第一区域的基板和在其间具有通道的第二区域，其中所述第一区域产生热载流子。存储单元还包括通道上方的栅极和包含第一电荷量的电荷捕获区域。限流器，其限制可流入通道的所产生的热载体的数量，其中限流器不控制第二区域的电压。

5. 发明授权

US06618290B1 Method of programming a non-volatile memory cell using a baking process 失效
标题翻译：使用烘烤过程对非易失性存储单元进行编程的方法
公开(公告)号：US06618290B1
公开(公告)日：2003-09-09
申请号：US09880366
申请日：2001-06-13
申请人： Janet S. Y. Wang , Narbeh Derhacobian
发明人： Janet S. Y. Wang , Narbeh Derhacobian
IPC分类号： G11C1604
CPC分类号： G11C16/0475
摘要： A method of programming that includes programming a fresh memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. Baking the programmed fresh cell causing a charge loss in the channel while the remaining charge within the channel is distributed more locally at the first region when compared to the distribution of charge prior to the baking.
摘要翻译：一种编程方法，包括用包括第一区域和第二区域以及沟道上方的栅极的衬底编程新鲜存储器单元以及包含第一电荷量的电荷捕获区域。烘烤编程的新鲜细胞，导致通道中的电荷损失，而与烘焙前的电荷分布相比，通道内的剩余电荷在第一区域更局部分布。

6. 发明授权

US06331953B1 Intelligent ramped gate and ramped drain erasure for non-volatile memory cells 有权
标题翻译：非易失性存储单元的智能斜坡栅极和斜坡漏极擦除
公开(公告)号：US06331953B1
公开(公告)日：2001-12-18
申请号：US09697813
申请日：2000-10-26
申请人： Janet S. Y. Wang , Narbeh Derhacobian , Daniel Sobek
发明人： Janet S. Y. Wang , Narbeh Derhacobian , Daniel Sobek
IPC分类号： G11C700
CPC分类号： G11C16/344 , G11C11/5671 , G11C16/0475 , G11C16/14 , G11C16/3445 , H01L29/7923
摘要： A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes: applying a voltage across the gate and the first region in accordance with a coarse erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region; and applying a voltage across the gate and the first region in accordance with a fine erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region.
摘要翻译：一种擦除存储单元的方法，该存储单元包括第一区域和第二区域以及通道之间的通道，以及包含第一电荷量的电荷捕获区域。该方法包括：根据粗略擦除电压序列施加跨栅极和第一区域的电压，使得第一电荷量的一部分从电荷捕获区域去除; 以及根据电压的精细擦除序列施加跨越栅极和第一区域的电压，使得第一电荷量的一部分从电荷捕获区域去除。

7. 发明授权

US06266281B1 Method of erasing non-volatile memory cells 有权
标题翻译：擦除非易失性存储单元的方法
公开(公告)号：US06266281B1
公开(公告)日：2001-07-24
申请号：US09504695
申请日：2000-02-16
申请人： Narbeth Derhacobian , Michael Van Buskirk , Daniel Sobeck , Janet S. Y. Wang , Chi Chang
发明人： Narbeth Derhacobian , Michael Van Buskirk , Daniel Sobeck , Janet S. Y. Wang , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/14 , G11C11/5671 , G11C16/0475
摘要： A method of erasing a memory cell that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a first voltage across the gate and the first region so that a first portion of the initial amount of charge is removed from the charge trapping region. Next, a second voltage is applied across the gate and the first region so that a second portion of the initial amount of charge is removed from the charge trapping region, wherein the second voltage is different than the first voltage.
摘要翻译：一种擦除具有第一区域和第二区域以及沟道上方的栅极的存储单元的方法，以及包含初始电荷量的电荷捕获区域。该方法包括跨越栅极和第一区域施加第一电压，使得初始电荷量的第一部分从电荷俘获区域移除。接下来，跨越栅极和第一区域施加第二电压，使得初始电荷量的第二部分从电荷捕获区域去除，其中第二电压不同于第一电压。

8. 发明授权

US06490205B1 Method of erasing a non-volatile memory cell using a substrate bias 有权
标题翻译：使用衬底偏置擦除非易失性存储单元的方法
公开(公告)号：US06490205B1
公开(公告)日：2002-12-03
申请号：US09697814
申请日：2000-10-26
申请人： Janet S. Y. Wang , Ravi S. Sunkavalli
发明人： Janet S. Y. Wang , Ravi S. Sunkavalli
IPC分类号： G11C1604
CPC分类号： G11C16/14 , G11C16/0475
摘要： A method of erasing a memory cell with a substrate that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a constant first voltage across the gate and applying a second constant voltage across said the region. A third constant voltage is applied in a region of the substrate outside of the first and second regions so that a first portion of the first amount of charge is removed from the charge trapping region.
摘要翻译：一种用具有第一区域和第二区域以及沟道上方的栅极的衬底擦除存储单元的方法，以及包含初始电荷量的电荷捕获区域。该方法包括跨越栅极施加恒定的第一电压并在所述区域上施加第二恒定电压。在第一和第二区域外部的衬底的区域中施加第三恒定电压，使得第一电荷量的第一部分从电荷捕获区域去除。

9. 发明授权

US06459618B1 Method of programming a non-volatile memory cell using a drain bias 有权
标题翻译：使用漏极偏置来编程非易失性存储单元的方法
公开(公告)号：US06459618B1
公开(公告)日：2002-10-01
申请号：US09880367
申请日：2001-06-13
申请人： Janet S. Y. Wang
发明人： Janet S. Y. Wang
IPC分类号： G11C1604
CPC分类号： G11C11/5671 , G11C16/0475 , H01L29/7923
摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate and applying a second constant voltage across the first region so as to generate a first charge injection region. The application of the second constant voltage is discontinued while simultaneously applying a third constant voltage across the first region so that a second charge injection region is generated that is larger than the first charge injection region.
摘要翻译：一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。该方法包括在栅极上施加恒定的第一电压并在第一区域上施加第二恒定电压，以产生第一电荷注入区域。停止施加第二恒定电压，同时在第一区域上施加第三恒定电压，使得产生大于第一电荷注入区域的第二电荷注入区域。

10. 发明授权

US06456531B1 Method of drain avalanche programming of a non-volatile memory cell 有权
标题翻译：非易失性存储器单元的排水雪崩编程方法
公开(公告)号：US06456531B1
公开(公告)日：2002-09-24
申请号：US09884402
申请日：2001-06-19
申请人： Janet S. Y. Wang , Sameer S. Haddad
发明人： Janet S. Y. Wang , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/12
摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region, and applying a third constant voltage across the second region that is near the avalanche breakdown voltage of the second region so that spillover electrons are significantly reduced in number within the channel when compared to if the third constant voltage is well below the avalanche breakdown voltage.
摘要翻译：一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。该方法包括跨越栅极施加恒定的第一电压，在第一区域上施加第二恒定电压，以及跨越第二区域施加第三恒定电压，该第二区域接近第二区域的雪崩击穿电压，使得溢出电子显着减少与第三恒定电压远低于雪崩击穿电压相比，在通道内的数量。

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