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1. 发明授权

US06590811B1 Higher program VT and faster programming rates based on improved erase methods 失效
公开(公告)号：US06590811B1
公开(公告)日：2003-07-08
申请号：US10173262
申请日：2002-06-17
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S. Y. Wang , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Janet S. Y. Wang , Kulachet Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C29/50004
摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

2. 发明授权

US06307784B1 Negative gate erase 有权
标题翻译：负栅极擦除
公开(公告)号：US06307784B1
公开(公告)日：2001-10-23
申请号：US09795856
申请日：2001-02-28
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Kulachet Tanpairoj , Ravi Sunkavalli
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Kulachet Tanpairoj , Ravi Sunkavalli
IPC分类号： G11C1600
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/0475 , G11C16/3404 , G11C16/344 , G11C16/3445 , H01L27/115
摘要： A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.
摘要翻译：用于执行验证擦除的方法和系统包括对一个扇区中的每个I / O提供实质上高的电场的擦除脉冲。该操作对于单个电源设备是重要的，因为整个阵列的擦除频带到带电流的开始大于由排水泵提供的带电流。在第一个擦除脉冲之后，可以在所有IO上一起执行擦除验证程序。在一个特定示例中，选择Vdrain电压处于基本上高的正电压，并且Vgate电压的值处于基本上高的负电压，其中Vdrain和Vgate之间的电压电位也是基本上高的电压。

3. 发明授权

US06493261B1 Single bit array edges 有权
标题翻译：单位阵列边缘
公开(公告)号：US06493261B1
公开(公告)日：2002-12-10
申请号：US09795865
申请日：2001-02-28
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian , Michael A. Van Buskirk
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian , Michael A. Van Buskirk
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/0475 , G11C16/0491 , G11C16/16 , G11C16/3404 , G11C16/344 , G11C16/3445 , H01L27/115
摘要： Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.
摘要翻译：在制造外边缘列时形成的存储单元的虚拟柱被连接到扇区等的实际使用的存储单元。虚拟存储单元的列通过在正常编程和擦除周期期间浮置伪存储单元来补偿，或者通过编程和擦除虚存储单元以及扇区中的实际使用的存储单元来补偿。通过处理类似于实际使用的电池的虚拟存储器单元，在制造和正常操作期间泄漏到虚拟电池中的电荷在较高应力温度和/或由于客户操作的寿命而具有有害影响的基本上被消除。

4. 发明授权

US06442074B1 Tailored erase method using higher program VT and higher negative gate erase 有权
标题翻译：使用更高程序VT和更高的负栅极擦除进行定制擦除方法
公开(公告)号：US06442074B1
公开(公告)日：2002-08-27
申请号：US09795854
申请日：2001-02-28
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/344 , G11C16/3445 , G11C29/50
摘要： A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO's together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.
摘要翻译：用于编程和擦除双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT和擦除脉冲进行编程来实现，该擦除脉冲为扇区1中的每个I / O提供基本上高的电场一次在第一个擦除脉冲之后，擦除验证程序在所有IO上一起执行。基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。选择提供基本上高的电场的擦除脉冲，以消除整个阵列的频带电流，其大于由排水泵提供的频带电流。

5. 发明授权

US06775187B1 Method of programming a dual cell memory device 失效
标题翻译：编程双单元存储器件的方法
公开(公告)号：US06775187B1
公开(公告)日：2004-08-10
申请号：US10422489
申请日：2003-04-24
申请人： Darlene G. Hamilton , Edward F. Runnion , Edward Hsia , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Edward F. Runnion , Edward Hsia , Kulachet Tanpairoj
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0475
摘要： A method of programming a dual cell memory device having a first charge storing cell and second charge storing cell. The first charge storing cell can be pre-read to determine if the first charge storing cell stores an amount of charge to increase a threshold voltage of the memory device over a specified threshold voltage. If not, the second charge storing cell can be programmed with a standard program pulse. If so, the second charge storing cell can be programed with a modified program pulse.
摘要翻译：一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。可以预先读取第一电荷存储单元，以确定第一电荷存储单元是否存储一定量的电荷以增加存储器件的阈值电压超过指定的阈值电压。如果不是，则可以用标准编程脉冲编程第二电荷存储单元。如果是这样，则可以用修改的编程脉冲对第二电荷存储单元进行编程。

6. 发明授权

US07652919B2 Multi-level operation in dual element cells using a supplemental programming level 有权
标题翻译：使用补充编程级别对双元素单元进行多级操作
公开(公告)号：US07652919B2
公开(公告)日：2010-01-26
申请号：US11771961
申请日：2007-06-29
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Fatima Bathul , Ou Li
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Fatima Bathul , Ou Li
IPC分类号： G11C11/34
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C16/3418 , G11C16/3427
摘要： The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells in a memory device. In multi-bit memory cells, programming one element can affect the second element. Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge level is programmed into a first element while a second element of the same memory cell is unprogrammed. Memory cell elements can be programmed using additional charge levels to mitigate such effects. For example, the sixteen distinct element combinations possible using four charge levels can be mapped to a subset of twenty-five possible element combinations using five charge levels, avoiding element combinations likely to generate excessive complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb.
摘要翻译：所要求保护的主题提供了便于在存储器件中编程和读取多级多位存储器单元的系统和/或方法。在多位存储器单元中，编程一个元件可以影响第二个元件。元件的某些组合可能导致过多的互补位干扰，状态依赖的不均匀电荷损失和状态相关的程序干扰，从而降低存储器件的可靠性。当高电荷电平被编程到第一元件中而同一存储器单元的第二元件未被编程时，这种效果可能是显着的。可以使用额外的电荷电平对存储单元元件进行编程，以减轻这种影响。例如，使用四个电荷电平可能的十六个不同元件组合可以被映射到使用五个电荷电平的二十五个可能元件组合的子集，避免可能产生过多的互补位干扰，状态依赖的非均匀电荷损失的元件组合，和状态依赖程序干扰。

7. 发明授权

US06956768B2 Method of programming dual cell memory device to store multiple data states per cell 有权
标题翻译：编程双单元存储器件以存储每个单元的多个数据状态的方法
公开(公告)号：US06956768B2
公开(公告)日：2005-10-18
申请号：US10413800
申请日：2003-04-15
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Edward Hsia , Yi He
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Edward Hsia , Yi He
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10
摘要： A method of programming a multi-level, dual cell memory device. The method includes independently programming a first charge storing cell and a second charge storing cell to respective data states, the data states selected from a blank program level or one of a plurality of charged program levels. Also disclosed is a method of reading the multi-level, dual cell memory device using a plurality of reference currents.
摘要翻译：一种编程多级双电池存储器件的方法。该方法包括将第一电荷存储单元和第二电荷存储单元独立地编程为相应的数据状态，从空白程序级或多个带电程序级中的一个选择的数据状态。还公开了一种使用多个参考电流读取多电平双电池存储器件的方法。

8. 发明授权

US06822909B1 Method of controlling program threshold voltage distribution of a dual cell memory device 有权
标题翻译：控制双电池存储器件的程序阈值电压分布的方法
公开(公告)号：US06822909B1
公开(公告)日：2004-11-23
申请号：US10422090
申请日：2003-04-24
申请人： Darlene G. Hamilton , Edward Hsia , Mark W. Randolph , Edward F. Runnion , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Edward Hsia , Mark W. Randolph , Edward F. Runnion , Kulachet Tanpairoj
IPC分类号： G11C1134
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/3454
摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.
摘要翻译：一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。该方法可以包括将初始编程脉冲施加到存储器件; 将存储器件的阈值电压与验证阈值电压进行比较; 并且如果所述存储器件的阈值电压小于所述验证阈值电压，则向所述存储器件施加第二编程脉冲，在所述存储器件期间，从所述初始编程脉冲修改所述第二编程脉冲的至少一个条件。

9. 发明授权

US06967873B2 Memory device and method using positive gate stress to recover overerased cell 有权
公开(公告)号：US06967873B2
公开(公告)日：2005-11-22
申请号：US10677790
申请日：2003-10-02
申请人： Darlene G. Hamilton , Zhizheng Liu , Mark W. Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
发明人： Darlene G. Hamilton , Zhizheng Liu , Mark W. Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
IPC分类号： G11C16/04 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

10. 发明授权

US06512701B1 Erase method for dual bit virtual ground flash 有权
标题翻译：双位虚拟接地闪存的擦除方法
公开(公告)号：US06512701B1
公开(公告)日：2003-01-28
申请号：US09886861
申请日：2001-06-21
申请人： Darlene G. Hamilton , Kulachet Tanpairoj , Yider Wu
发明人： Darlene G. Hamilton , Kulachet Tanpairoj , Yider Wu
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C16/0475 , G11C16/0491
摘要： A system and methodology is provided for verifying erasure of one or more dual bit virtual ground memory cells in a memory device, such as a flash memory. Each of the dual bits have a first or normal bit and a second or complimentary bit associated with the first or normal bit. The system and methodology include verifying and erasure of both a normal bit and a complimentary bit of the cell. The erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell. The set of erase pulses is comprised of a two sided erase pulse to both sides of the bits in the cell or transistor junction followed by a first single sided erase pulse to one side and a second single sided erase pulse to the other side of transistor junction.
摘要翻译：提供了用于验证擦除存储器设备（例如闪存）中的一个或多个双位虚拟接地存储器单元的系统和方法。每个双位具有与第一或正常位相关联的第一或正常位和第二或补充位。系统和方法包括验证和擦除单元的正常位和互补位。擦除包括将一组擦除脉冲施加到单个双位单元中的正常位和补充位。该组擦除脉冲由单元或晶体管结中的位的两侧的双侧擦除脉冲组成，之后是一侧的第一单侧擦除脉冲和到晶体管结的另一侧的第二单侧擦除脉冲。

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