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1. 发明授权

US07853634B2 Digital signal processing circuit having a SIMD circuit 有权
标题翻译：具有SIMD电路的数字信号处理电路
公开(公告)号：US07853634B2
公开(公告)日：2010-12-14
申请号：US11433331
申请日：2006-05-12
申请人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
发明人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.
摘要翻译：公开了具有单指令多数据（SIMD）的集成电路（IC）。 SIMD电路包括：由第一操作码控制的多个复用器; 以及耦合到所述多个多路复用器并由第二操作码控制的算术逻辑单元（ALU）; 并且其中所述ALU具有多个加法器，其中所述多个加法器由所述第二操作码的某些位控制，并且其中所述多个加法器中的第一加法器添加多个输入位以产生第一求和位和第一进位位所述第一加法器与所述多个加法器的其它加法器同时运行。

2. 发明授权

US07840627B2 Digital signal processing circuit having input register blocks 有权
标题翻译：具有输入寄存器块的数字信号处理电路
公开(公告)号：US07840627B2
公开(公告)日：2010-11-23
申请号：US11432823
申请日：2006-05-12
申请人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
发明人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.
摘要翻译：一种集成电路，包括具有耦合到第一算术逻辑单元（ALU）电路的第一和第二寄存器块的数字信号处理元件（DSPE）; 与顶部DSPE相邻的中间DSPE具有耦合到第二ALU电路的第三和第四寄存器块，其中第三寄存器块耦合到第一寄存器块，并且第四寄存器块寄存器块耦合到第二寄存器块 ; 以及与中间DSPE相邻的底部DSPE，具有耦合到第三ALU电路的第五和第六寄存器块，其中第五寄存器块耦合到第三寄存器块，并且第六寄存器块寄存器块耦合到第四寄存器块。

3. 发明授权

US07567997B2 Applications of cascading DSP slices 有权
标题翻译：级联DSP片的应用
公开(公告)号：US07567997B2
公开(公告)日：2009-07-28
申请号：US11019518
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/48
CPC分类号： G06F7/5443
摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
摘要翻译：在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。该IC允许实现一些基本的数学函数，例如加，减，乘和除。可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。

4. 发明授权

US07184466B1 Radio frequency data conveyance system including configurable integrated circuits 有权
标题翻译：包括可配置集成电路的射频数据传送系统
公开(公告)号：US07184466B1
公开(公告)日：2007-02-27
申请号：US10243411
申请日：2002-09-12
申请人： Brian K. Seemann , Brian T. Brunn , Normand T. Lemay, Jr. , Daniel J. Ferris, III , Thomas Anthony Lee , James M. Simkins , David B. Squires
发明人： Brian K. Seemann , Brian T. Brunn , Normand T. Lemay, Jr. , Daniel J. Ferris, III , Thomas Anthony Lee , James M. Simkins , David B. Squires
IPC分类号： H04B1/38
CPC分类号： H04B1/406 , H04B1/0003
摘要： A data conveyance integrated system that can be utilized in a base station and/or end user devices in a wireless communication system. The integrated system includes first and second integrated circuits (ICs). The first IC includes a first serial-deserial (SERDES) module, a transmit radio frequency module, and a receive radio frequency module. The transmit and receive radio frequency modules provide the wireless communication between the base stations and end user devices. The second IC includes a second SERDES module and a programmable logic fabric programmed to implement one or more wireless communication functions. Accordingly, the programmable logic fabric generates outbound digital signals from data (e.g., video, audio, control, or text data) provided to the device, and/or processes inbound digital signals to recapture the originally transmitted data. Thus, base stations and/or end user devices within a wireless communication system can be readily reconfigured.
摘要翻译：一种可在无线通信系统中的基站和/或终端用户设备中使用的数据传输集成系统。集成系统包括第一和第二集成电路（IC）。第一IC包括第一串并联（SERDES）模块，发射射频模块和接收射频模块。发射和接收射频模块提供基站和终端用户设备之间的无线通信。第二IC包括被编程为实现一个或多个无线通信功能的第二SERDES模块和可编程逻辑结构。因此，可编程逻辑结构从提供给设备的数据（例如，视频，音频，控制或文本数据）生成出站数字信号，和/或处理入站数字信号以重新捕获原始传输的数据。因此，可以容易地重新配置无线通信系统内的基站和/或终端用户设备。

5. 发明授权

US08104012B1 System and methods for reducing clock power in integrated circuits 有权
标题翻译：集成电路中降低时钟功率的系统和方法
公开(公告)号：US08104012B1
公开(公告)日：2012-01-24
申请号：US12363721
申请日：2009-01-31
申请人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
发明人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/62
摘要： Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.
摘要翻译：在诸如现场可编程门阵列（FPGA）或复杂可编程逻辑器件（CPLD）的可编程逻辑器件（PLD）中实现动态功率节省和资源的有效利用，通过接收指定包括时钟信号，时钟缓冲器的电路的设计网表，时钟使能信号和同步元件，检查设计网表以识别耦合到公共时钟和时钟使能信号的同步元件，将时钟信号切割到同步元件以形成修改后的设计网表，将门控时钟缓冲器插入修改的网表以输出门控时钟信号到同步元件，响应于时钟使能信号，并在修改的网表上执行放置和布线。提供了一种用于在EDA工具上执行该方法的系统。可以将这些方法提供为存储在计算机可读介质上的可执行指令，其使可编程处理器执行该方法。

6. 发明授权

US07844653B2 Digital signal processing circuit having a pre-adder circuit 有权
标题翻译：具有预加法器电路的数字信号处理电路
公开(公告)号：US07844653B2
公开(公告)日：2010-11-30
申请号：US11432848
申请日：2006-05-12
申请人： James M. Simkins , John M. Thendean , Vasisht Mantra Vadi , Bernard J. New , Jennifer Wong , Anna Wing Wah Wong , Alvin Y. Ching
发明人： James M. Simkins , John M. Thendean , Vasisht Mantra Vadi , Bernard J. New , Jennifer Wong , Anna Wing Wah Wong , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.
摘要翻译：具有预加法器电路的数字信号处理电路包括：耦合到乘法器电路和一组多路复用器的第一寄存器块和预加法器电路，其中多路复用器组由操作码控制，并且其中预加法器电路具有第一加法器电路; 以及具有第二加法器电路并耦合到所述多路复用器组的算术逻辑单元（ALU）。

7. 发明授权

US07797610B1 Method and apparatus for virtual quad-port random access memory 有权
标题翻译：虚拟四端口随机存取存储器的方法和装置
公开(公告)号：US07797610B1
公开(公告)日：2010-09-14
申请号：US11184310
申请日：2005-07-19
申请人： James M. Simkins
发明人： James M. Simkins
IPC分类号： G11C29/00
CPC分类号： G11C8/16 , G11C29/52 , G11C2029/0409
摘要： Embedded logic circuits in combination with a configurable logic resources on a common integrated circuit facilitates over-clocked operation of embedded, dual-port memory blocks. The implementation yields fully independent and simultaneous read/write access to the dual-port memory blocks from the configurable logic on each clock cycle of the configurable logic. Error detection/correction and data scrubbing is also facilitated by the embedded logic circuits, such that error detection/correction is completely transparent to the configurable logic, while data scrubbing is performed with minimal degradation to the memory access bandwidth of the configurable logic.
摘要翻译：嵌入式逻辑电路与公共集成电路上的可配置逻辑资源相结合，有助于嵌入式双端口存储器块的超时操作。该实现在可配置逻辑的每个时钟周期上从可配置逻辑获得完全独立且同时的读/写访问双端口存储器块。嵌入式逻辑电路也促进了错误检测/校正和数据擦除，使得错误检测/校正对于可配置逻辑完全透明，同时以可配置逻辑的存储器访问带宽的最小程度的降低来执行数据擦除。

8. 发明授权

US07161995B1 Method and apparatus for Viterbi synchronization 有权
标题翻译：维特比同步的方法和装置
公开(公告)号：US07161995B1
公开(公告)日：2007-01-09
申请号：US10098282
申请日：2002-03-15
申请人： Raied N. Mazahreh , Edwin J. Hemphill , James M. Simkins
发明人： Raied N. Mazahreh , Edwin J. Hemphill , James M. Simkins
IPC分类号： H04B1/66
CPC分类号： H03M13/41 , H04L1/0054
摘要： Method and apparatus are described for determining when a convolution decoder is out of synchronization. Normalizations from a convolutional decoder are counted to provide a normalization count, and errors from the convolutional decoder are counted to provide an error count. One of the normalization count and the error count is compared to a first threshold associated with the selected one of the normalization count and the error count. The other of the normalization count and the error count is compared to a second threshold in response to meeting the first threshold, such as bit errors per X normalizations or normalizations per Y bit errors. From this latter comparison, an indicator is generated as to whether the convolutional decoder is synchronized or not.
摘要翻译：描述了用于确定卷积解码器何时不同步的方法和装置。计数来自卷积解码器的归一化以提供归一化计数，并且对来自卷积解码器的错误进行计数以提供错误计数。将归一化计数和错误计数之一与与所选归一化计数和错误计数中的一个相关联的第一阈值进行比较。响应于满足第一阈值将归一化计数和错误计数中的另一个与第二阈值进行比较，例如每X标准化的位错误或每Y位错误的归一化。根据后一种比较，产生关于卷积解码器是否同步的指示符。

9. 发明授权

US08495122B2 Programmable device with dynamic DSP architecture 有权
标题翻译：具有动态DSP架构的可编程器件
公开(公告)号：US08495122B2
公开(公告)日：2013-07-23
申请号：US11019735
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个片包括一个模式端口，它接收模式控制信号，用于动态地改变相关片段的功能和连通性。这种改变可以在或不配置PLD的情况下发生。

10. 发明授权

US08479133B2 Method of and circuit for implementing a filter in an integrated circuit 有权
标题翻译：在集成电路中实现滤波器的方法和电路
公开(公告)号：US08479133B2
公开(公告)日：2013-07-02
申请号：US12418979
申请日：2009-04-06
申请人： Xavier Wendling , James M. Simkins
发明人： Xavier Wendling , James M. Simkins
IPC分类号： G06F17/50
CPC分类号： G06F7/575 , H03H17/06 , H03H2017/0692
摘要： According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; and transforming the filter of the high level design to a filter using a processing block of the circuit configured to accommodate a common coefficient, wherein the processing block is coupled to receive taps associated with the common coefficient. A computer program product and a circuit for configuring a filter in a circuit to be implemented in an integrated circuit are also disclosed.
摘要翻译：根据本发明的实施例，公开了一种在集成电路中实现的电路中配置滤波器的方法。该方法包括接收电路的高级设计; 识别高级设计中的过滤器; 分析滤波器的系数; 以及使用被配置为容纳公共系数的所述电路的处理块将所述高级设计的所述滤波器变换为滤波器，其中所述处理块被耦合以接收与所述公共系数相关联的抽头。还公开了一种用于在集成电路中实现的电路中配置滤波器的计算机程序产品和电路。

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