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1. 发明授权

US07567997B2 Applications of cascading DSP slices 有权
标题翻译：级联DSP片的应用
公开(公告)号：US07567997B2
公开(公告)日：2009-07-28
申请号：US11019518
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/48
CPC分类号： G06F7/5443
摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
摘要翻译：在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。该IC允许实现一些基本的数学函数，例如加，减，乘和除。可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。

2. 发明授权

US08495122B2 Programmable device with dynamic DSP architecture 有权
标题翻译：具有动态DSP架构的可编程器件
公开(公告)号：US08495122B2
公开(公告)日：2013-07-23
申请号：US11019735
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个片包括一个模式端口，它接收模式控制信号，用于动态地改变相关片段的功能和连通性。这种改变可以在或不配置PLD的情况下发生。

3. 发明授权

US07472155B2 Programmable logic device with cascading DSP slices 有权
标题翻译：具有级联DSP片的可编程逻辑器件
公开(公告)号：US07472155B2
公开(公告)日：2008-12-30
申请号：US11019783
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , G06F15/7867 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个DSP片包括多个操作数输入端口和片输出端口，所有这些端口都可编程地连接到通用路由和逻辑资源。操作数端口接收处理的操作数，切片输出端口传送处理结果。每个切片还包括连接到相应切片输出端口的反馈端口，以支持在该实施例中的累积功能，以及连接到上游切片的输出端口以支持级联的级联输入端口。

4. 发明授权

US07467175B2 Programmable logic device with pipelined DSP slices 有权
标题翻译：可编程逻辑器件，带流水线DSP片
公开(公告)号：US07467175B2
公开(公告)日：2008-12-16
申请号：US11019782
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以组合的DSP片段，以创建不同大小和复杂度的DSP电路。根据一些实施例的DSP片段包括可被配置为从零到两个时钟周期引入不同量的延迟的可编程操作数输入寄存器，例如以支持流水线化。在一个这样的实施例中，每个DSP片包括具有乘法器端口，被乘数端口和产品端口的部分乘积生成器。乘法器和被乘数端口通过相应的第一和第二操作数输入寄存器连接到操作数输入端口，每个第一和第二操作数输入寄存器能够从零延迟到两个延迟的时钟周期。在另一个实施例中，至少一个操作数输入寄存器的输出可以连接到下游DSP片的操作数输入寄存器的输入，使得操作数可以在一个或多个片之间传送。

5. 发明授权

US07480690B2 Arithmetic circuit with multiplexed addend inputs 有权
标题翻译：具有复用加法输入的算术电路
公开(公告)号：US07480690B2
公开(公告)日：2009-01-20
申请号：US11019854
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/48
CPC分类号： G06F7/509
摘要： Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.
摘要翻译：描述的是算术电路，逻辑上分为乘积发生器和加法器。逻辑上位于产品发生器和加法器之间的多路复用电路通过提供来自产品发生器的部分乘积到加法器的末端来支持常规功能。还可以控制复用电路以将多个外部添加的输入引导到加法器。附加加数输入可以包括从其他算术电路级联的输入和输出。

6. 发明授权

US07467177B2 Mathematical circuit with dynamic rounding 有权
标题翻译：具有动态四舍五入的数学电路
公开(公告)号：US07467177B2
公开(公告)日：2008-12-16
申请号：US11019853
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： G06F7/49963
摘要： Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.
摘要翻译：描述了执行灵活舍入方案的数学电路。这些电路需要很少的额外资源，并且可以动态调整以改变舍入所涉及的位数。在一个实施例中，DSP电路存储从二进制数2（M-1）和2（M-1）-1组中选择的舍入常数，计算校正因子，并将舍入常数，校正因子和一个数据项以获得舍入的数据项。

7. 发明授权

US07853634B2 Digital signal processing circuit having a SIMD circuit 有权
标题翻译：具有SIMD电路的数字信号处理电路
公开(公告)号：US07853634B2
公开(公告)日：2010-12-14
申请号：US11433331
申请日：2006-05-12
申请人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
发明人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.
摘要翻译：公开了具有单指令多数据（SIMD）的集成电路（IC）。 SIMD电路包括：由第一操作码控制的多个复用器; 以及耦合到所述多个多路复用器并由第二操作码控制的算术逻辑单元（ALU）; 并且其中所述ALU具有多个加法器，其中所述多个加法器由所述第二操作码的某些位控制，并且其中所述多个加法器中的第一加法器添加多个输入位以产生第一求和位和第一进位位所述第一加法器与所述多个加法器的其它加法器同时运行。

8. 发明授权

US07840627B2 Digital signal processing circuit having input register blocks 有权
标题翻译：具有输入寄存器块的数字信号处理电路
公开(公告)号：US07840627B2
公开(公告)日：2010-11-23
申请号：US11432823
申请日：2006-05-12
申请人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
发明人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.
摘要翻译：一种集成电路，包括具有耦合到第一算术逻辑单元（ALU）电路的第一和第二寄存器块的数字信号处理元件（DSPE）; 与顶部DSPE相邻的中间DSPE具有耦合到第二ALU电路的第三和第四寄存器块，其中第三寄存器块耦合到第一寄存器块，并且第四寄存器块寄存器块耦合到第二寄存器块 ; 以及与中间DSPE相邻的底部DSPE，具有耦合到第三ALU电路的第五和第六寄存器块，其中第五寄存器块耦合到第三寄存器块，并且第六寄存器块寄存器块耦合到第四寄存器块。

9. 发明授权

US07844653B2 Digital signal processing circuit having a pre-adder circuit 有权
标题翻译：具有预加法器电路的数字信号处理电路
公开(公告)号：US07844653B2
公开(公告)日：2010-11-30
申请号：US11432848
申请日：2006-05-12
申请人： James M. Simkins , John M. Thendean , Vasisht Mantra Vadi , Bernard J. New , Jennifer Wong , Anna Wing Wah Wong , Alvin Y. Ching
发明人： James M. Simkins , John M. Thendean , Vasisht Mantra Vadi , Bernard J. New , Jennifer Wong , Anna Wing Wah Wong , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.
摘要翻译：具有预加法器电路的数字信号处理电路包括：耦合到乘法器电路和一组多路复用器的第一寄存器块和预加法器电路，其中多路复用器组由操作码控制，并且其中预加法器电路具有第一加法器电路; 以及具有第二加法器电路并耦合到所述多路复用器组的算术逻辑单元（ALU）。

10. 发明授权

US07882165B2 Digital signal processing element having an arithmetic logic unit 有权
标题翻译：具有算术逻辑单元的数字信号处理单元
公开(公告)号：US07882165B2
公开(公告)日：2011-02-01
申请号：US11408364
申请日：2006-04-21
申请人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi , David P. Schultz
发明人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi , David P. Schultz
IPC分类号： G06F7/38
CPC分类号： G06K9/00986 , G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , H03K19/1737
摘要： A digital signal processing circuit including: a multiplier circuit; a plurality of multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.
摘要翻译：一种数字信号处理电路，包括：乘法器电路; 耦合到所述乘法电路并由第一操作码控制的多个多路复用器; 以及耦合到多个多路复用器并由第二操作码控制的算术逻辑单元。

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