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1. 发明授权

US07161995B1 Method and apparatus for Viterbi synchronization 有权
标题翻译：维特比同步的方法和装置
公开(公告)号：US07161995B1
公开(公告)日：2007-01-09
申请号：US10098282
申请日：2002-03-15
申请人： Raied N. Mazahreh , Edwin J. Hemphill , James M. Simkins
发明人： Raied N. Mazahreh , Edwin J. Hemphill , James M. Simkins
IPC分类号： H04B1/66
CPC分类号： H03M13/41 , H04L1/0054
摘要： Method and apparatus are described for determining when a convolution decoder is out of synchronization. Normalizations from a convolutional decoder are counted to provide a normalization count, and errors from the convolutional decoder are counted to provide an error count. One of the normalization count and the error count is compared to a first threshold associated with the selected one of the normalization count and the error count. The other of the normalization count and the error count is compared to a second threshold in response to meeting the first threshold, such as bit errors per X normalizations or normalizations per Y bit errors. From this latter comparison, an indicator is generated as to whether the convolutional decoder is synchronized or not.
摘要翻译：描述了用于确定卷积解码器何时不同步的方法和装置。计数来自卷积解码器的归一化以提供归一化计数，并且对来自卷积解码器的错误进行计数以提供错误计数。将归一化计数和错误计数之一与与所选归一化计数和错误计数中的一个相关联的第一阈值进行比较。响应于满足第一阈值将归一化计数和错误计数中的另一个与第二阈值进行比较，例如每X标准化的位错误或每Y位错误的归一化。根据后一种比较，产生关于卷积解码器是否同步的指示符。

2. 发明授权

US07100101B1 Method and apparatus for concatenated and interleaved turbo product code encoding and decoding 有权
标题翻译：用于级联和交织的turbo产品代码编码和解码的方法和装置
公开(公告)号：US07100101B1
公开(公告)日：2006-08-29
申请号：US10291441
申请日：2002-11-08
申请人： Edwin J. Hemphill , James M. Simkins , Raied N. Mazahreh
发明人： Edwin J. Hemphill , James M. Simkins , Raied N. Mazahreh
IPC分类号： H03M13/27 , H03M13/29 , H03M13/39 , H03M13/45
CPC分类号： H03M13/2972 , H03M13/19 , H03M13/29 , H03M13/2909 , H03M13/296 , H03M13/2966
摘要： Method and apparatus for concatenated and interleaved turbo product code (TPC) encoding and decoding are described. Described are series concatenated and interleaved TPC encoders and decoders. One or more combinations of these encoders and decoders may be combined to provide a coder/decoder (CODEC). Such a CODEC may be used for communicating information between a computer and a network via a data channel.
摘要翻译：描述了用于级联和交织的涡轮乘积码（TPC）编码和解码的方法和装置。串联和交错的TPC编码器和解码器是描述的。可以组合这些编码器和解码器的一个或多个组合来提供编码器/解码器（CODEC）。这样的CODEC可以用于经由数据信道在计算机和网络之间传送信息。

3. 发明授权

US07266757B1 Pipelined architecture implementing recursion processes for forward error correction 有权
标题翻译：流水线架构实现前向纠错的递归过程
公开(公告)号：US07266757B1
公开(公告)日：2007-09-04
申请号：US10769662
申请日：2004-01-29
申请人： Raied N. Mazahreh , Edwin J. Hemphill
发明人： Raied N. Mazahreh , Edwin J. Hemphill
IPC分类号： H03M13/03
CPC分类号： H03M13/2957 , H03M13/3905 , H03M13/3972
摘要： A method and apparatus for performing a recursion process on a data block for error correction. The disclosure describes concurrently operating pipelined sub-processes that decode the data block with error correction. The pipelined sub-processes are implemented as sub-circuits of an integrated circuit. The output data from each sub-process is stored for input by a subsequent sub-process of the pipelined sub-processes.
摘要翻译：一种用于对数据块执行递归处理以进行纠错的方法和装置。本公开描述了同时操作对具有错误校正的数据块进行解码的流水线子进程。流水线子流程被实现为集成电路的子电路。来自每个子过程的输出数据被存储以供流水线子进程的后续子过程输入。

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