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1. 发明申请

US20060184946A1 Thread priority method, apparatus, and computer program product for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
标题翻译：线程优先方法，装置和计算机程序产品，用于确保同时多线程微处理器的处理公平性
公开(公告)号：US20060184946A1
公开(公告)日：2006-08-17
申请号：US11055850
申请日：2005-02-11
申请人： James Bishop , Hung Le , Dung Nguyen , Balaram Sinharoy , Brian Thompto , Raymond Yeung
发明人： James Bishop , Hung Le , Dung Nguyen , Balaram Sinharoy , Brian Thompto , Raymond Yeung
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4818 , G06F9/485
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.
摘要翻译：在数据处理系统中公开了一种方法，装置和计算机程序产品，用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性。在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

2. 发明申请

US20060184767A1 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions 有权
标题翻译：动态重新计算依赖指令转向问题队列中的资源向量
公开(公告)号：US20060184767A1
公开(公告)日：2006-08-17
申请号：US11056691
申请日：2005-02-11
申请人： Hung Le , Dung Nguyen , Brian Thompto , Raymond Yeung
发明人： Hung Le , Dung Nguyen , Brian Thompto , Raymond Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3836
摘要： A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.
摘要翻译：一种用于在问题时刻动态地转向指令的方法和装置，以便最大化由SMT处理器处理的多个线程共享的执行单元的使用效率。在发布时使用资源向量将来自正在被处理的线程的指令重定向到多个线程正在竞争的共享资源。分析用于发行排队的指令的现有资源向量，并在适当情况下动态重新计算和修改以最大限度地提高效率。

3. 发明申请

US20060179282A1 Method using hazard vector to enhance issue throughput of dependent instructions in a microprocessor 失效
标题翻译：使用危险向量的方法来增强微处理器中依赖指令的问题吞吐量
公开(公告)号：US20060179282A1
公开(公告)日：2006-08-10
申请号：US11054289
申请日：2005-02-09
申请人： Hung Le , Dung Nguyen , Raymond Yeung
发明人： Hung Le , Dung Nguyen , Raymond Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3834 , G06F9/3838 , G06F9/3867
摘要： A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively. R and W bits corresponding to the specified register are used to ensure that a store instruction does not read data from, and that a load instruction does not write data to the specified register, respectively, before the first instruction is moved to the final write back stage.
摘要翻译：提供了一种用于具有多个寄存器的处理器的方法和相关装置，其中顺序地发出指令以从初始阶段到最终回写阶段移动经过一系列执行阶段。作为一种方法，实施例包括发出诸如FMA指令的第一指令以移动经过执行级序列的步骤，第一指令被引导到指定的一个寄存器。该方法还包括发出第二指令以移动通过执行阶段，第二指令在第一指令发出之后但在第一指令到达最终回写阶段之前发出。第二条指令同样针对指定的寄存器，并且选择性地包括存储指令或加载指令。使用与指定寄存器相对应的R和W位来确保存储指令不会从第一指令移动到最终回写之前分别读取数据，并且加载指令不会将数据写入指定的寄存器阶段。

4. 发明申请

US20060179100A1 System and method for performing floating point store folding 失效
标题翻译：执行浮点存储折叠的系统和方法
公开(公告)号：US20060179100A1
公开(公告)日：2006-08-10
申请号：US11054686
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3826 , G06F9/30014 , G06F9/3824 , G06F9/3838 , G06F9/3885
摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.
摘要翻译：一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

5. 发明申请

US20060168393A1 Apparatus and method for dependency tracking and register file bypass controls using a scannable register file 审中-公开
标题翻译：使用可扫描寄存器文件的依赖关系跟踪和寄存器文件旁路控制的装置和方法
公开(公告)号：US20060168393A1
公开(公告)日：2006-07-27
申请号：US11044567
申请日：2005-01-27
申请人： Bjorn Christensen , Peter Klim , Dung Nguyen , Raymond Yeung
发明人： Bjorn Christensen , Peter Klim , Dung Nguyen , Raymond Yeung
IPC分类号： G06F12/14
CPC分类号： G06F9/30141 , G06F9/30134 , G06F9/3828 , G06F9/3838 , G06F9/3867
摘要： An apparatus and method for dependency tracking and register file bypass controls using a scannable register file are provided. With the apparatus and method, a scannable register file array is provided and used to track the stage of any instruction in the execution unit. Every entry in the target vector is updated every cycle to stay synchronized with the instructions in the execution unit. To keep the register file array synchronized with the instructions in the execution unit, a right shift of all the data in each entry of the register file array occurs every cycle. The scan port of the register file array cells is used as the shift function.
摘要翻译：提供了使用可扫描寄存器文件的依赖关系跟踪和寄存器文件旁路控制的装置和方法。利用该装置和方法，提供可扫描的寄存器文件阵列并用于跟踪执行单元中任何指令的阶段。每个周期更新目标向量中的每个条目，以与执行单元中的指令保持同步。为了使寄存器文件阵列与执行单元中的指令保持同步，每个周期都会发生寄存器文件阵列的每个条目中所有数据的右移。寄存器文件阵列单元的扫描端口用作移位功能。

6. 发明申请

US20060179286A1 System and method for processing limited out-of-order execution of floating point loads 审中-公开
标题翻译：用于处理浮点负载有限次序执行的系统和方法
公开(公告)号：US20060179286A1
公开(公告)日：2006-08-10
申请号：US11054201
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F9/44
CPC分类号： G06F9/3867 , G06F9/3838
摘要： A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.
摘要翻译：用于执行浮点负载有限次序执行的系统。该系统包括构成管道的多个阶段，这些阶段包括早期阶段。该系统还包括用于将算术指令输入流水线的机构，算术指令包括结果地址。该机制还确定在将算术指令的结果写入结果地址之前，算术指令是否在写入（WAW）条件之后发生写入。确定包括将结果地址与在流水线中的算术指令之后的加载指令相关联的加载地址进行比较。与加载指令相关联的加载数据在管道的早期阶段被写入加载地址。如果结果地址等于加载地址，则会发生WAW条件。响应于发生的WAW状态，写入算术指令的结果被抑制。

7. 发明申请

US20110116764A1 NON-DESTRUCTIVE FILE BASED MASTERING FOR MULTIPLE LANGUAGES AND VERSIONS 有权
标题翻译：多种语言和版本的基于非破坏性文件的MASTERING MASTERING FOR MULTIPLE LANGUAGES AND VERSIONS
公开(公告)号：US20110116764A1
公开(公告)日：2011-05-19
申请号：US12947642
申请日：2010-11-16
申请人： Arjun Ramamurthy , Geoffrey A. Bloder , Raymond Yeung
发明人： Arjun Ramamurthy , Geoffrey A. Bloder , Raymond Yeung
IPC分类号： H04N5/92
CPC分类号： H04N21/854 , G06F9/454 , G11B27/034 , G11B27/036 , G11B27/28 , H04N21/47205 , H04N21/4884
摘要： A method, system, apparatus, article of manufacture, and computer program product provide the ability to non-destructively generate a file based master. A domestic source (having domestic audio and video content) with textless content (have portions of the domestic source that is devoid of text) is obtained. A localized source (e.g., localized audio-video) based on the domestic source is received. The localized video is compared to the domestic source to determine differences. The localized video is bladed and realigned with the domestic source. Metadata (of the differences) is transposed onto the domestic source. Texted portions in the domestic source are obscured with corresponding portions of the textless content. Texted material (based on the localized video and texted portions) is created. The localized video content and the textless content are discarded. The domestic source, localized audio content, created texted material; and metadata are combined into a playlist that represents a localized file based master.
摘要翻译：方法，系统，装置，制品和计算机程序产品提供非破坏性地生成基于文件的主机的能力。获得具有无文本内容的国内来源（具有国内音频和视频内容）（具有国内来源的部分文本）。接收到基于国内来源的本地化源（例如，本地化音频视频）。将本地化视频与国内来源进行比较以确定差异。本地化视频是由国内来源进行刀片和重新排列的。元数据（差异）转移到国内来源。国内来源中的短信部分与无文本内容的相应部分模糊。创建了短信材质（基于本地化视频和短信部分）。本地化的视频内容和无文本内容被丢弃。国内来源，本地化音频内容，制作了短信材质; 并将元数据组合成表示基于本地化文件的主机的播放列表。

8. 发明申请

US20060285119A1 Active control and detection of two nearly orthogonal polarizations in a fiber for heterodyne interferometry 失效
标题翻译：主动控制和检测光纤中两个几乎正交的极化，用于外差干涉测量
公开(公告)号：US20060285119A1
公开(公告)日：2006-12-21
申请号：US11156103
申请日：2005-06-17
申请人： Joanne Law , Raymond Yeung , Eric Johnstone , Kerry Bagwell
发明人： Joanne Law , Raymond Yeung , Eric Johnstone , Kerry Bagwell
IPC分类号： G01B9/02
CPC分类号： G01B9/02003 , G01B2290/70
摘要： A polarization control system includes a light source that generates two light beams with different polarization states and optical frequencies. A polarization state modulator changes the polarization states of the two light beams. A first detector path generates a first beat signal from the two light beams passing through a first polarizer. A second detector path generates a second beat signal from the two light beams passing through a second polarizer that is oriented substantially orthogonal to the first polarizer. An amplitude detector generates an amplitude beat signal from the first and the second beat signals. The system then uses the amplitude beat signal to determine how to adjust the polarization state modulator in order to generate the first and the second light beams with the desired polarization states.
摘要翻译：偏振控制系统包括产生具有不同偏振态和光频的两个光束的光源。偏振状态调制器改变两个光束的偏振状态。第一检测器路径从穿过第一偏振器的两个光束产生第一拍动信号。第二检测器路径从穿过基本上正交于第一偏振器的第二偏振器的两个光束产生第二拍动信号。振幅检测器从第一和第二拍频信号产生幅度差信号。系统然后使用幅度差拍信号来确定如何调整偏振状态调制器，以便产生具有所需偏振态的第一和第二光束。

9. 发明授权

US07869662B2 System architecture for sensing an absolute position using a target pattern 有权
标题翻译：使用目标模式感测绝对位置的系统架构
公开(公告)号：US07869662B2
公开(公告)日：2011-01-11
申请号：US11778813
申请日：2007-07-17
申请人： Janet Yun , David C. Chu , Matthew D. Tenuta , Raymond Yeung , Nhan T. Nguyen
发明人： Janet Yun , David C. Chu , Matthew D. Tenuta , Raymond Yeung , Nhan T. Nguyen
IPC分类号： G06K9/36
CPC分类号： G01B11/002 , G06F3/0321 , G06F3/0346
摘要： A location system and a location system on a chip (LCoS) and method are described.
摘要翻译：描述了位置系统和芯片上的位置系统（LCoS）和方法。

10. 发明申请

US20080291470A1 SYSTEM ARCHITECTURE FOR SENSING AN ABSOLUTE POSITION USING A TARGET PATTERN 有权
标题翻译：使用目标图形感测绝对位置的系统架构
公开(公告)号：US20080291470A1
公开(公告)日：2008-11-27
申请号：US11778813
申请日：2007-07-17
申请人： Janet Yun , David C. Chu , Matthew D. Tenuta , Raymond Yeung , Nhan T. Nguyen
发明人： Janet Yun , David C. Chu , Matthew D. Tenuta , Raymond Yeung , Nhan T. Nguyen
IPC分类号： G01B11/14
CPC分类号： G01B11/002 , G06F3/0321 , G06F3/0346
摘要： A location system and a location system on a chip (LCoS) and method are described.
摘要翻译：描述了位置系统和芯片上的位置系统（LCoS）和方法。

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