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1. 发明申请

US20080091928A1 Branch lookahead prefetch for microprocessors 有权
标题翻译：用于微处理器的分支前瞻预取
公开(公告)号：US20080091928A1
公开(公告)日：2008-04-17
申请号：US11953799
申请日：2007-12-10
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and determining the validity of data utilized by the speculative execution. Dispatch logic determines the validity of the data by marking one or more registers of an instruction dispatch unit to indicate which results of the pending instructions are invalid. The speculative execution of instructions can occur across multiple pipeline stages of the microprocessor, and the validity of the data is tracked during their execution in the multiple pipeline stages while monitoring a dependency of the speculatively executed instructions relative to one another during their execution in the multiple pipeline stages.
摘要翻译：一种处理微处理器中的程序指令的方法，其通过在执行程序指令期间检测到失速状态的发生来减少与错误预测的分支指令相关联的延迟，推测性地执行一个或多个未决指令，其中包括在失速期间包括至少一个分支指令条件，并确定投机执行使用的数据的有效性。调度逻辑通过标记指令调度单元的一个或多个寄存器来指示待处理指令的哪些结果无效来确定数据的有效性。指令的推测执行可以在微处理器的多个流水线阶段发生，并且在多个流水线阶段的执行期间跟踪数据的有效性，同时在多个流水线阶段的执行期间监视推测性执行的指令相对于彼此的依赖性流水线阶段

2. 发明申请

US20060184946A1 Thread priority method, apparatus, and computer program product for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
标题翻译：线程优先方法，装置和计算机程序产品，用于确保同时多线程微处理器的处理公平性
公开(公告)号：US20060184946A1
公开(公告)日：2006-08-17
申请号：US11055850
申请日：2005-02-11
申请人： James Bishop , Hung Le , Dung Nguyen , Balaram Sinharoy , Brian Thompto , Raymond Yeung
发明人： James Bishop , Hung Le , Dung Nguyen , Balaram Sinharoy , Brian Thompto , Raymond Yeung
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4818 , G06F9/485
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors that concurrently execute multiple threads during each clock cycle. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles. The clock cycle priority is assigned according to a standard selection definition during the standard selection state by selecting the first thread to be a primary thread and the second thread to be a secondary thread during the standard selection state. If a condition exists that requires overriding the standard selection definition, an override state is executed during which the standard selection definition is overridden by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.
摘要翻译：在数据处理系统中公开了一种方法，装置和计算机程序产品，用于确保在每个时钟周期期间同时执行多个线程的同时多线程（SMT）微处理器中的处理公平性。在持续预期数量的时钟周期的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。在标准选择状态期间，根据标准选择定义分配时钟周期优先级，通过在标准选择状态期间选择作为主线程的第一线程和第二线程作为次线程。如果存在需要覆盖标准选择定义的条件，则执行超越状态，在该状态期间，通过选择第二个线程作为主线程，并将第一个线程作为次要线程来覆盖标准选择定义。超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

3. 发明申请

US20060149935A1 Load lookahead prefetch for microprocessors 失效
公开(公告)号：US20060149935A1
公开(公告)日：2006-07-06
申请号：US11016236
申请日：2004-12-17
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838 , G06F9/3851
摘要： The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled. In this speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available via forwarding and are not written to the architected registers. A set of status bits are used to dynamically keep track of the dependencies between instructions in the pipeline and a bit vector tracks invalid architected facilities with respect to the speculative instruction stream. Both sources of information are used to identify load instructions with valid operands for calculating the load address. If the operands are valid, then a load prefetch operation is started to retrieve data from the cache ahead of time such that it can be available for the load instruction when it is non-speculatively executed.

4. 发明申请

US20060184769A1 Localized generation of global flush requests while guaranteeing forward progress of a processor 审中-公开
标题翻译：本地化的全局刷新请求，同时保证处理器的进度
公开(公告)号：US20060184769A1
公开(公告)日：2006-08-17
申请号：US11056692
申请日：2005-02-11
申请人： Michael Floyd , Hung Le , Larry Leitner , Brian Thompto
发明人： Michael Floyd , Hung Le , Larry Leitner , Brian Thompto
IPC分类号： G06F9/40
CPC分类号： G06F9/3867 , G06F9/3814 , G06F9/3836 , G06F9/3859
摘要： Localized generation of global flush requests while providing a means for increasing the likelihood of forward progress in a controlled fashion. Local hazard (error) detection is accomplished with a trigger network situated between execution units and configurable state machines that track trigger events. Once a hazardous state is detected, a local detection mechanism requests a workaround flush from the flush control logic. The processor is flushed and a centralized workaround control is informed of the workaround flush. The centralized control blocks subsequent workaround flushes until forward progress has been made. The centralized control can also optionally send out a control to activate a set of localized workarounds or reduced performance modes to avoid the hazardous condition once instructions are re-executed after the flush until a configurable amount of forward progress has been made.
摘要翻译：本地化的全球冲刷请求，同时提供了一种增加以受控方式推进进展的可能性的手段。本地危险（错误）检测是通过位于执行单元和跟踪触发事件的可配置状态机之间的触发网络完成的。一旦检测到危险状态，本地检测机制就会从刷新控制逻辑请求解决冲突。处理器被刷新，并且通知了一个集中的解决方法控制措施。集中式控制块后续的解决方法会刷新，直到进行进一步的进展。集中式控制还可以选择性地发送控制以激活一组本地化的解决方案或降低的性能模式，以避免在冲洗之后重新执行指令直到可配置的前进进度为止的危险状况。

5. 发明申请

US20060184767A1 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions 有权
标题翻译：动态重新计算依赖指令转向问题队列中的资源向量
公开(公告)号：US20060184767A1
公开(公告)日：2006-08-17
申请号：US11056691
申请日：2005-02-11
申请人： Hung Le , Dung Nguyen , Brian Thompto , Raymond Yeung
发明人： Hung Le , Dung Nguyen , Brian Thompto , Raymond Yeung
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3836
摘要： A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.
摘要翻译：一种用于在问题时刻动态地转向指令的方法和装置，以便最大化由SMT处理器处理的多个线程共享的执行单元的使用效率。在发布时使用资源向量将来自正在被处理的线程的指令重定向到多个线程正在竞争的共享资源。分析用于发行排队的指令的现有资源向量，并在适当情况下动态重新计算和修改以最大限度地提高效率。

6. 发明申请

US20060184771A1 Mini-refresh processor recovery as bug workaround method using existing recovery hardware 审中-公开
标题翻译：微型刷新处理器恢复作为使用现有恢复硬件的错误解决方法
公开(公告)号：US20060184771A1
公开(公告)日：2006-08-17
申请号：US11055823
申请日：2005-02-11
申请人： Michael Floyd , Larry Leitner , Sheldon Levenstein , Scott Swaney , Brian Thompto
发明人： Michael Floyd , Larry Leitner , Sheldon Levenstein , Scott Swaney , Brian Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3863 , G06F9/3851
摘要： A method in a data processing system for avoiding a microprocessor's design defects and recovering a microprocessor from failing due to design defects, the method comprised of the following steps: The method detects and reports of events which warn of an error. Then the method locks a current checkpointed state and prevents instructions not checkpointed from checkpointing. After that, the method releases checkpointed state stores to a L2 cache, and drops stores not checkpointed. Next, the method blocks interrupts until recovery is completed. Then the method disables the power savings states throughout the processor. After that, the method disables an instruction fetch and an instruction dispatch. Next, the method sends a hardware reset signal. Then the method restores selected registers from the current checkpointed state. Next, the method fetches instructions from restored instruction addresses. Then the method resumes a normal execution after a programmable number of instructions.
摘要翻译：一种用于避免微处理器设计缺陷并由于设计缺陷而使微处理器故障恢复的数据处理系统中的方法，该方法包括以下步骤：该方法检测并报告发生错误的事件。然后，该方法锁定当前的检查点状态，并防止从检查点进行检查点的指令。之后，该方法将检查点状态存储发送到L2缓存，并且将不检查点丢弃存储。接下来，该方法将阻止中断，直到恢复完成。然后该方法将禁用整个处理器的省电状态。之后，该方法禁用指令提取和指令分派。接下来，该方法发送硬件复位信号。然后，该方法将从当前检查点状态恢复所选寄存器。接下来，该方法从恢复的指令地址获取指令。然后，该方法在可编程指令数量之后恢复正常执行。

7. 发明申请

US20080077776A1 Load Lookahead Prefetch for Microprocessors 有权
标题翻译：加载用于微处理器的前瞻预取
公开(公告)号：US20080077776A1
公开(公告)日：2008-03-27
申请号：US11950495
申请日：2007-12-05
申请人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemeyer , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838 , G06F9/3851
摘要： The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled. In this speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available via forwarding and are not written to the architected registers. A set of status bits are used to dynamically keep track of the dependencies between instructions in the pipeline and a bit vector tracks invalid architected facilities with respect to the speculative instruction stream. Both sources of information are used to identify load instructions with valid operands for calculating the load address. If the operands are valid, then a load prefetch operation is started to retrieve data from the cache ahead of time such that it can be available for the load instruction when it is non-speculatively executed.
摘要翻译：本发明允许微处理器在失速状态期间识别并推测性地执行未来的加载指令。这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。可以从远程高速缓存或主存储器预取这样的未来加载指令的数据，使得当停止条件到期之后，当加载指令被重新执行（不推测执行）时，其数据将驻留在L1高速缓存中，或者将进入处理器，导致执行时间缩短。当检测到扩展失速条件时，启动加载前瞻预取，允许推测执行通常已经停止的指令。在这种推测模式中，由于缺少L1高速缓存的源负载，设备在推测执行模式下不可用的设备，或由于不能通过转发而不能使用并且未写入到架构化寄存器的推测性指令结果，指令操作数可能无效。一组状态位用于动态地跟踪流水线中的指令之间的依赖关系，并且位向量相对于推测性指令流跟踪无效的架构设施。两个信息来源用于识别加载指令，其中包含用于计算加载地址的有效操作数。如果操作数有效，则启动加载预取操作以提前从高速缓存中检索数据，使得当非推测性地执行加载指令时，可以对加载指令可用。

8. 发明申请

US20060184778A1 Systems and methods for branch target fencing 失效
标题翻译：分支目标围栏的系统和方法
公开(公告)号：US20060184778A1
公开(公告)日：2006-08-17
申请号：US11056512
申请日：2005-02-11
申请人： David Levitan , Brian Thompto
发明人： David Levitan , Brian Thompto
IPC分类号： G06F9/44
CPC分类号： G06F9/3804 , G06F9/3814 , G06F9/3842 , G06F9/3844 , G06F9/3861
摘要： Systems and methods for handling the event of a wrong branch prediction and an instruction rejection in a digital processor are disclosed. More particularly, hardware and software are disclosed for detecting a condition where a branch instruction was mispredicted and an instruction that preceded the branch instruction is rejected after the branch instruction is executed. When the condition is detected, the branch instruction and rejected instruction are recirculated for execution. Until, the branch instruction is re-executed, control circuitry can prevent instructions from being received into an instruction buffer that feeds instructions to the execution units of the processor by fencing the instruction buffer from the fetcher. The instruction fetcher may continue fetching instructions along the branch target path into a local cache until the fence is dropped.
摘要翻译：公开了用于处理数字处理器中错误分支预测和指令拒绝的事件的系统和方法。更具体地，公开了用于检测分支指令被错误预测的条件并且在执行分支指令之后拒绝分支指令之前的指令的硬件和软件。当检测到条件时，分支指令和拒绝指令被再循环以执行。直到分支指令被重新执行为止，控制电路可以防止指令被接收到指令缓冲器中，指令缓冲器通过从提取器中击打指令缓冲器来将指令馈送到处理器的执行单元。指令读取器可以继续沿着分支目标路径获取指令到本地高速缓存中，直到栅栏被丢弃。

9. 发明申请

US20060184770A1 Method of implementing precise, localized hardware-error workarounds under centralized control 审中-公开
标题翻译：在集中控制下实施精确的本地化硬件错误解决方法的方法
公开(公告)号：US20060184770A1
公开(公告)日：2006-08-17
申请号：US11056878
申请日：2005-02-12
申请人： James Bishop , Michael Floyd , Hung Le , Larry Leitner , Brian Thompto
发明人： James Bishop , Michael Floyd , Hung Le , Larry Leitner , Brian Thompto
IPC分类号： G06F9/40
CPC分类号： G06F11/0793 , G06F11/0721
摘要： In a processor, a localized workaround is activated upon the sensing of a problematic condition occurring on said processor, and then control of the deactivation of the localized workaround is superseded by a centralized controller. In a preferred embodiment, the centralized controller monitors forward progress of the processor and maintains the workaround in an active condition until a threshold level of forward progress has occurred. Optionally, the localized workaround may be re-activated while under centralized control, resetting the notion of forward progress. Using the present invention, localized workarounds perform effectively while having a minimal impact on processor performance.
摘要翻译：在处理器中，当感测到在所述处理器上发生的有问题的状况时激活本地化解决方案，然后由集中式控制器取代对本地化解决方案的停用的控制。在优选实施例中，集中控制器监视处理器的前进进程，并将解决方案维持在活动状态，直到发生了前进进程的阈值级别。可选地，本地化的解决方法可以在集中控制的情况下被重新激活，重置前进进程的概念。使用本发明，本地化的解决方法在对处理器性能具有最小影响的同时有效地执行。

10. 发明申请

US20060149934A1 Using a modified value GPR to enhance lookahead prefetch 失效
标题翻译：使用修改值GPR来增强前瞻预取
公开(公告)号：US20060149934A1
公开(公告)日：2006-07-06
申请号：US11016206
申请日：2004-12-17
申请人： Richard Eickemever , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
发明人： Richard Eickemever , Hung Le , Dung Nguyen , Benjamin Stolt , Brian Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838
摘要： The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch. In speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available. Dependency and dirty (i.e. invalid result) bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions will then use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers will be used.
摘要翻译：本发明允许微处理器在失速状态期间识别和推测地执行未来的指令。这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。这样的未来指令的执行可以启动来自远程高速缓存或主存储器的数据或指令的预取，或以其他方式通过指令流进行进展。以这种方式，当在停止条件到期之后重新执行（不推测地执行）指令时，它们将以降低的执行延迟执行; 例如通过访问预取到L1高速缓存中的数据，或者进入处理器，或通过在推测性地解决的误预测分支之后执行目标指令。在推测模式中，由于缺少L1缓存的源加载，在推测执行模式下不可用的设备，或由于不可用的推测指令结果，指令操作数可能无效。跟踪依赖关系和脏（即无效结果）位，并用于确定哪些推测指令对执行有效。改进的值寄存器存储和位向量被用于提高推测结果的可用性，否则，由于不能将其写入到架构化的寄存器，否则将抛弃执行流水线。修改后的通用寄存器用于在对应指令到达回写时存储推测结果，修改后的位向量跟踪存储在其中的结果。当修改的位向量中的相应位指示数据已被修改时，不直接从旧指令旁路的较小的推测指令将使用该修改的数据。否则，将使用来自架构化寄存器的数据。

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