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1. 发明申请

US20060091442A1 Out of the box vertical transistor for eDRAM on SOI 失效
公开(公告)号：US20060091442A1
公开(公告)日：2006-05-04
申请号：US11298800
申请日：2005-12-09
申请人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
发明人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L29/94
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

2. 发明申请

US20050247966A1 OUT OF THE BOX VERTICAL TRANSISTOR FOR eDRAM ON SOI 有权
标题翻译：在SOI上用于eDRAM的盒式垂直晶体管
公开(公告)号：US20050247966A1
公开(公告)日：2005-11-10
申请号：US10709450
申请日：2004-05-06
申请人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
发明人： James Adkisson , Gary Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl Radens
IPC分类号： H01L21/8242 , H01L27/108 , H01L31/119
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.
摘要翻译：本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件掩埋氧化层。上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

3. 发明申请

US20070296006A1 STRUCTURE FOR PIXEL SENSOR CELL THAT COLLECTS ELECTRONS AND HOLES 失效
标题翻译：用于收集电子和孔的像素传感器单元的结构
公开(公告)号：US20070296006A1
公开(公告)日：2007-12-27
申请号：US11850776
申请日：2007-09-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
IPC分类号： H01L31/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281 , H01L31/1037
摘要： The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明涉及一种像素传感器单元的设计结构。像素传感器单元对于给定的光量大约使可用信号加倍。具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上，以及p型收集阱区域用于收集由撞击光子产生的孔的基板的表面。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

4. 发明申请

US20070259500A1 Structure Having Isolation Structure Including Deuterium Within A Substrate And Related Method 审中-公开
标题翻译：具有包含氘底物的隔离结构的结构及相关方法
公开(公告)号：US20070259500A1
公开(公告)日：2007-11-08
申请号：US11381861
申请日：2006-05-05
申请人： Kangguo Cheng , Oh-Jung Kwon , Deok-Kee Kim , James Adkisson
发明人： Kangguo Cheng , Oh-Jung Kwon , Deok-Kee Kim , James Adkisson
IPC分类号： H01L21/336 , H01L21/76 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/3003 , H01L21/76283 , H01L21/823481 , H01L29/66772 , H01L29/78 , H01L29/78654
摘要： Structures having an isolation structure including deuterium and a related method are disclosed. The deuterium is preferably substantially uniformly distributed, and has a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. One structure includes a substrate for a semiconductor device including an isolation structure within the substrate, the isolation structure including substantially uniformly distributed deuterium in a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. The substrate may include a semiconductor-on-insulator substrate. A method may include the steps of: providing an isolation structure in a substrate, the isolation structure including deuterium; and annealing to diffuse the deuterium into the substrate (prior to and/or after forming a gate dielectric). The structures and method provide a more efficient means for incorporating deuterium and reducing defects. In addition, the deuterium anneal can occur prior to gate dielectric formation during front-end-of-line processes, such that the anneal temperature can be high to improve deuterium incorporation with reduced anneal time.
摘要翻译：公开了具有包括氘的隔离结构的结构和相关方法。氘优选基本上均匀分布，并且具有大于在天然存在的氢气中发现的浓度（基于总氢原子含量）。一种结构包括用于半导体器件的衬底，该衬底包括衬底内的隔离结构，该隔离结构包括基本上均匀分布的氘，其浓度（基于总氢原子含量）大于在天然存在的氢中发现的浓度。衬底可以包括绝缘体上半导体衬底。一种方法可以包括以下步骤：在衬底中提供隔离结构，所述隔离结构包括氘; 和退火以将氘扩散到衬底中（在形成栅极电介质之前和/或之后）。结构和方法提供了一种更有效的方法来引入氘和减少缺陷。此外，氘退火可以在前端工艺过程中的栅极电介质形成之前发生，使得退火温度可以高以改善氘掺杂并减少退火时间。

5. 发明申请

US20070145438A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20070145438A1
公开(公告)日：2007-06-28
申请号：US11681454
申请日：2007-03-02
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

6. 发明申请

US20070138380A1 FUNNELED LIGHT PIPE FOR PIXEL SENSORS 有权
标题翻译：用于像素传感器的FUNNELED LIGHT PIPE
公开(公告)号：US20070138380A1
公开(公告)日：2007-06-21
申请号：US11275171
申请日：2005-12-16
申请人： James Adkisson , Jeffrey Gambino , Robert Leidy , Richard Rassel
发明人： James Adkisson , Jeffrey Gambino , Robert Leidy , Richard Rassel
IPC分类号： G01J1/04
CPC分类号： G01J1/04 , G01J1/0407 , G01J1/0422 , G01J1/0488
摘要： A photo sensing structure and methods for forming the same. The structure includes (a) a semiconductor substrate and (b) a photo collection region on the semiconductor substrate. The structure also includes a funneled light pipe on top of the photo collection region. The funneled light pipe includes (i) a bottom cylindrical portion on top of the photo collection region of the photo collection region, and (ii) a funneled portion which has a tapered shape and is on top and in direct physical contact with the bottom cylindrical portion. The structure further includes a color filter region on top of the funneled light pipe.
摘要翻译：感光结构及其形成方法。该结构包括（a）半导体衬底和（b）半导体衬底上的光收集区域。该结构还包括在照片收集区域顶部的漏斗光管。漏斗式光管包括（i）照片收集区域的照片收集区域顶部的底部圆柱形部分，和（ii）具有锥形形状并且在顶部并与底部圆柱体直接物理接触的漏斗部分一部分。该结构还包括在漏斗的光管的顶部上的滤色器区域。

7. 发明申请

US20070102738A1 LIGHT SHIELD FOR CMOS IMAGER 有权
标题翻译： CMOS成像器的光栅
公开(公告)号：US20070102738A1
公开(公告)日：2007-05-10
申请号：US11164072
申请日：2005-11-09
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe
IPC分类号： H01L31/113 , H01L31/062
CPC分类号： H01L27/14623 , H01L27/14685
摘要： The present invention provides a light shield for shielding the floating diffusion of a complementary metal-oxide semiconductor (CMOS) imager. In accordance with an embodiment of the present invention, there is provided a pixel sensor cell including: a device region formed on a substrate; and a first layer of material forming a sidewall adjacent to a side of the device region for blocking electromagnetic radiation from the device region.
摘要翻译：本发明提供一种用于屏蔽互补金属氧化物半导体（CMOS）成像器的浮动扩散的遮光罩。根据本发明的实施例，提供了一种像素传感器单元，包括：形成在基板上的器件区域; 以及形成与所述器件区域的一侧相邻的侧壁的第一材料层，用于阻挡来自所述器件区域的电磁辐射。

8. 发明申请

US20060128126A1 MASKED SIDEWALL IMPLANT FOR IMAGE SENSOR 有权
标题翻译：用于图像传感器的嵌入式平板植入体
公开(公告)号：US20060128126A1
公开(公告)日：2006-06-15
申请号：US10905043
申请日：2004-12-13
申请人： James Adkisson , Mark Jaffe , Arthur Johnson , Robert Leidy , Jeffrey Maling
发明人： James Adkisson , Mark Jaffe , Arthur Johnson , Robert Leidy , Jeffrey Maling
IPC分类号： H01L21/425
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14687 , H01L27/14689
摘要： A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.
摘要翻译：形成在第一导电类型的衬底上的新型图像传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成沟槽隔离区域。该结构包括掺杂区域，该掺杂剂区域包括沿着隔离区域的侧壁形成的第一导电类型的材料，其适于将钉扎层电耦合到衬底。相应的方法通过首先制造光致抗蚀剂层并且通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来促进掺杂剂材料在隔离区域侧壁中的成角度的离子注入。为了促进通过抗蚀剂阻挡掩模的侧壁边缘的成角度注入，提出了两种方法：1）成像光致抗蚀剂的间隔物型蚀刻; 或2）成像光致抗蚀剂的角溅射工艺。

9. 发明申请

US20060113622A1 A DAMASCENE COPPER WIRING IMAGE SENSOR 有权
标题翻译： DAMASCENE铜接线图像传感器
公开(公告)号：US20060113622A1
公开(公告)日：2006-06-01
申请号：US10904807
申请日：2004-11-30
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Anthony Stamper
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Anthony Stamper
IPC分类号： H01L31/00
CPC分类号： H01L27/14685 , H01L21/76819 , H01L21/76834 , H01L21/76838 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14687
摘要： An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.
摘要翻译：一种图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。然后将蚀刻的开口用电介质材料重新填充。在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

10. 发明申请

US20070194397A1 PHOTO-SENSOR AND PIXEL ARRAY WITH BACKSIDE ILLUMINATION AND METHOD OF FORMING THE PHOTO-SENSOR 有权
标题翻译：具有背光照明的照相传感器和像素阵列以及形成照相传感器的方法
公开(公告)号：US20070194397A1
公开(公告)日：2007-08-23
申请号：US11276218
申请日：2006-02-17
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Alan Loiseau , Richard Rassel
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Alan Loiseau , Richard Rassel
IPC分类号： H01L31/0232 , H01L31/00
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/1463 , H01L27/1464 , H01L27/14689
摘要： An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.
摘要翻译：具有FET像素阵列的成像传感器和形成成像传感器的方法。每个像素是半导体岛，例如绝缘体上硅（SOI）晶片上的N型硅。 FET形成在一个光电二极管电极中，例如P阱阴极。滤色器可以附接到岛的相对表面。保护层（例如，玻璃或石英）或窗口在滤色器处固定到像素阵列。图像传感器可以从背面照亮，电池布线在电池单元上方。因此，通过保护层的光学信号被滤色器过滤并被相应的光电传感器选择性地感测。

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