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1. 发明申请

US20070238232A9 Transistor or semiconductor device and method of fabricating the same 有权
标题翻译：晶体管或半导体器件及其制造方法
公开(公告)号：US20070238232A9
公开(公告)日：2007-10-11
申请号：US11179971
申请日：2005-07-12
申请人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
发明人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/7785
摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.
摘要翻译：提供半导体器件的晶体管及其制造方法。晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层，所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。在这种结构中，可以提高晶体管的隔离和开关速度。此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

2. 发明申请

US20060105510A1 Transistor or semiconductor device and method of fabricating the same 有权
标题翻译：晶体管或半导体器件及其制造方法
公开(公告)号：US20060105510A1
公开(公告)日：2006-05-18
申请号：US11179971
申请日：2005-07-11
申请人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
发明人： Jae Mun , Jong Lim , Woo Chang , Hong Ji , Ho Ahn , Hae Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/7785
摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.
摘要翻译：提供半导体器件的晶体管及其制造方法。晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层，所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。在这种结构中，可以提高晶体管的隔离和开关速度。此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

3. 发明申请

US20060121658A1 Method of manufacturing field effect transistor 有权
标题翻译：制造场效应晶体管的方法
公开(公告)号：US20060121658A1
公开(公告)日：2006-06-08
申请号：US11180726
申请日：2005-07-14
申请人： Ho Ahn , Jong Lim , Hong Ji , Woo Chang , Jae Mun , Hae Kim
发明人： Ho Ahn , Jong Lim , Hong Ji , Woo Chang , Jae Mun , Hae Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/66856 , H01L29/66462
摘要： Provided is a method of manufacturing a field effect transistor (FET). The method includes steps of: forming an ohmic metal layer on a substrate in source and drain regions; sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein a lowermost resist pattern is exposed in the first region, and the insulating layer is exposed in the second region; exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns. In this method, transistors having different threshold voltages can be manufactured without additional mask patterns using the least number of processes, with the results that the cost of production can be reduced and the stability and productivity of semiconductor devices can be improved.
摘要翻译：提供了制造场效应晶体管（FET）的方法。该方法包括以下步骤：在源极和漏极区域的衬底上形成欧姆金属层; 在所得结构的整个表面上顺序地形成绝缘层和多层抗蚀剂层，并且同时形成除了欧姆金属层以外的第一区域和不包括欧姆金属层的第二区域中具有不同形状的抗蚀剂图案，其中最下面抗蚀剂图案在第一区域中暴露，并且绝缘层在第二区域中暴露; 通过分别使用抗蚀剂图案作为蚀刻掩模，同时蚀刻暴露的绝缘层和暴露的最下面的抗蚀剂图案来暴露衬底和绝缘层; 对曝光的衬底进行凹陷处理并蚀刻暴露的绝缘层以露出衬底; 以及在衬底上形成具有彼此不同蚀刻深度的栅极凹陷区域，沉积预定的栅极金属和去除抗蚀剂图案。在该方法中，可以使用最少数量的工艺来制造具有不同阈值电压的晶体管，而不需要额外的掩模图案，结果可以降低生产成本，并且可以提高半导体器件的稳定性和生产率。

4. 发明申请

US20070132514A1 Power device having connection structure compensating for reactance component of transmission line 失效
标题翻译：具有补偿传输线电抗分量的连接结构的功率器件
公开(公告)号：US20070132514A1
公开(公告)日：2007-06-14
申请号：US11519668
申请日：2006-09-12
申请人： Woo Chang , Jae Mun , Haecheon Kim , Jong Lim , Hong Ji , Ho Ahn
发明人： Woo Chang , Jae Mun , Haecheon Kim , Jong Lim , Hong Ji , Ho Ahn
IPC分类号： H03F3/68
CPC分类号： H03F3/602 , H03F3/211 , H03F2200/366 , H03F2200/447 , H03F2200/543 , H03F2203/21178
摘要： Provided is a power device having a connection structure compensating for a reactance component, in which transistors are arranged and connected to minimize deterioration of transistor properties caused by heat by compensating for a reactance component causing a phase difference due to transmission lines used for connecting a plurality of transistors in parallel such that the power device to be used for a high-frequency power amplifier outputs high power, and transmitting heat generated by high output power to a heat sink to be dissipated.
摘要翻译：提供了具有补偿电抗分量的连接结构的功率器件，其中配置并连接晶体管，以通过补偿导致由于用于连接多个元件的传输线引起的相位差的电抗分量来最小化由热引起的晶体管性质的劣化的晶体管并联，使得用于高频功率放大器的功率器件输出高功率，并将由高输出功率产生的热量传输到散热器。

5. 发明申请

US20070099368A1 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20070099368A1
公开(公告)日：2007-05-03
申请号：US11454721
申请日：2006-06-16
申请人： Ho Ahn , Jong Lim , Jae Mun , Hong Ji , Woo Chang , Hea Kim
发明人： Ho Ahn , Jong Lim , Jae Mun , Hong Ji , Woo Chang , Hea Kim
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L29/812 , H01L29/42316 , H01L29/66462 , H01L29/66856 , H01L29/778
摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.
摘要翻译：提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

6. 发明申请

US20050121694A1 COMPOUND SEMICONDUCTOR HIGH FREQUENCY SWITCH DEVICE 有权
标题翻译：复合半导体高频开关器件
公开(公告)号：US20050121694A1
公开(公告)日：2005-06-09
申请号：US10874396
申请日：2004-06-22
申请人： Jae Mun , Hong Ji , Hokyun Ahn , Heacheon Kim
发明人： Jae Mun , Hong Ji , Hokyun Ahn , Heacheon Kim
IPC分类号： H01L27/095 , H01L29/739 , H01L29/778 , H01L31/072
CPC分类号： H01L29/7785
摘要： A high frequency switch device includes an epitaxy substrate that is formed by sequentially stacking an AlGaAs/GaAs superlattic buffer layer, a first Si planar doping layer, an undoped first AlGaAs spacer, an undoped InGaAs layer, an undoped second AlGaAs spacer, a second Si planar doping layer having a doping density greater than that of the first Si planar doping layer, and an undoped GaAs/AlGaAs capping layer on a GaAs semi-insulated substrate. The undoped GaAs/AlGaAs capping layer is formed with a source electrode and a drain electrode that form an ohmic contact with the undoped GaAs/AlGaAs capping layer thereon, and a gate electrode formed between the source electrode and the drain electrode, thereby forming a Schottky contact with the undoped GaAs/AlGaAs capping layer.
摘要翻译：高频开关器件包括：通过依次层叠AlGaAs / GaAs超缓冲层，第一Si平面掺杂层，未掺杂的第一AlGaAs间隔物，未掺杂的InGaAs层，未掺杂的第二AlGaAs间隔物，第二Si 具有大于第一Si平面掺杂层的掺杂密度的平坦掺杂层和GaAs半绝缘衬底上的未掺杂的GaAs / AlGaAs覆盖层。未掺杂的GaAs / AlGaAs覆盖层形成有与其上的未掺杂的GaAs / AlGaAs覆盖层形成欧姆接触的源电极和漏电极，以及形成在源电极和漏电极之间的栅电极，由此形成肖特基与未掺杂的GaAs / AlGaAs覆盖层接触。

7. 发明授权

US07662375B2 Use of glucose-6-phosphate isomerase and antibodies thereto for the diagnosis and therapy of arthritis, and test of anti-arthritic compounds 有权
标题翻译：使用葡萄糖-6-磷酸异构酶及其抗体进行关节炎的诊断和治疗，并测定抗关节炎化合物
公开(公告)号：US07662375B2
公开(公告)日：2010-02-16
申请号：US11360515
申请日：2006-02-24
申请人： Christophe Benoist , Isao Matsumoto , Anne-Sophie Korganow , Diane Mathis , Mariana Maccioni , Hong Ji
发明人： Christophe Benoist , Isao Matsumoto , Anne-Sophie Korganow , Diane Mathis , Mariana Maccioni , Hong Ji
IPC分类号： A61K39/395 , A61K39/00 , G01N33/00 , C12P21/00
CPC分类号： G01N33/564 , G01N2333/992 , G01N2800/102
摘要： The present invention relates to the use of antibodies against glucose-6-phosphate isomerase (GPI) and like protein for diagnosis of arthritis and the use of said protein for treatment of arthritis. It is also aimed at a process for isolating monoclonal antibodies capable of transferring arthritis and antibodies thereof, as well as a method for determining the anti-arthritis potential of a composition.
摘要翻译：本发明涉及抗葡萄糖-6-磷酸异构酶（GPI）等抗体的抗体用于诊断关节炎和使用所述蛋白质治疗关节炎的用途。还涉及一种分离能够转移关节炎及其抗体的单克隆抗体的方法，以及用于测定组合物的抗关节炎潜力的方法。

8. 发明授权

US06259079B1 Microwave food package and method 有权
标题翻译：微波食品包装及方法
公开(公告)号：US06259079B1
公开(公告)日：2001-07-10
申请号：US09484283
申请日：2000-01-18
申请人： Hong Ji , Randal J. Monforton
发明人： Hong Ji , Randal J. Monforton
IPC分类号： H05B680
CPC分类号： B65D81/3469 , B65D2581/3421 , B65D2581/344 , B65D2581/3489 , B65D2581/349 , B65D2581/3491 , B65D2581/3493 , B65D2581/3494 , B65D2581/3498
摘要： Apparatus for and method of controlling heating of a foodstuff using microwave energy having a food package with a microwave shielding layer containing a plurality of apertures therein sized to permit entry of both evanescent microwave energy and propagating microwave energy into the interior of the package with the microwave shielding layer being moved outward as the package expands due to generation of water vapor such that an interior volume of the package is subsequently protected against substantial evanescent microwave irradiation of the foodstuff during completion of the microwave heating cycle using propagating microwave energy to further heat the foodstuff.
摘要翻译：使用微波能量控制食品加热的装置和方法，所述食品包装具有包含多个孔的微波屏蔽层，其尺寸允许消逝的微波能量和微波能量进入到具有微波的包装内部的微波能量屏蔽层随着封装由于水蒸气的产生而膨胀而向外移动，使得随后在使用传播的微波能量完成微波加热循环期间保护封装的内部容积免受食品的大量ev逝微波照射，从而进一步加热食品。

9. 发明授权

US06231903B1 Food package for microwave heating 有权
标题翻译：微波加热食品包装
公开(公告)号：US06231903B1
公开(公告)日：2001-05-15
申请号：US09248870
申请日：1999-02-11
申请人： Hong Ji , Randal J. Monforton
发明人： Hong Ji , Randal J. Monforton
IPC分类号： B65D8134
CPC分类号： B65D81/3469 , B65D2581/3421 , B65D2581/3489 , B65D2581/3494
摘要： A food package and method of controlling heating of a foodstuff within the food package using microwave energy wherein the food package has a microwave shielding layer containing a plurality of apertures therein sized to permit penetration of evanescent microwave energy into the interior of the package with the microwave shielding layer being moved outward as the package expands due to generation of water vapor such that an interior volume of the package is subsequently protected against substantial microwave irradiation of the foodstuff upon and beyond completion of the microwave heating cycle.
摘要翻译：一种食品包装和方法，其使用微波能量控制食品包装内的食品的加热，其中食品包装具有包含多个孔的微波屏蔽层，其尺寸允许微波能量通过微波穿透到包装内部随着包装由于水蒸气的产生而膨胀，屏蔽层向外移动，使得随后在微波加热循环完成之后保护包装的内部容积免受食品的大量微波照射。

10. 发明申请

US20070126518A1 Oscillator using TFMS line 审中-公开
标题翻译：振荡器采用TFMS线
公开(公告)号：US20070126518A1
公开(公告)日：2007-06-07
申请号：US11544629
申请日：2006-10-10
申请人： Hong Ji , Hea Kim , Kyoung Cho
发明人： Hong Ji , Hea Kim , Kyoung Cho
IPC分类号： H03B5/18
CPC分类号： H03B5/1847
摘要： Provided is an oscillator in which a resonator unit and an oscillator unit are coupled with each other using a thin film microstrip (TFMS) line to increase a line impedance and thus improve a phase noise characteristic. The oscillator includes a resonator unit resonating in a specific frequency band among variable frequencies, an oscillator unit generating an oscillation frequency using the resonance frequency, and a coupling unit coupling the resonator unit with the oscillator unit using a TFMS line.
摘要翻译：提供了一种振荡器，其中谐振器单元和振荡器单元使用薄膜微带线（TFMS）线彼此耦合以增加线路阻抗，从而提高相位噪声特性。振荡器包括在可变频率之中的特定频带中谐振的谐振器单元，使用谐振频率产生振荡频率的振荡器单元，以及使用TFMS线将振荡器单元与振荡器单元耦合的耦合单元。

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